C8051F704-GQR Silicon Labs, C8051F704-GQR Datasheet - Page 117
C8051F704-GQR
Manufacturer Part Number
C8051F704-GQR
Description
8-bit Microcontrollers - MCU 15kB 32B EEPROM ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F704-GQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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18.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 18.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 18.2). These modes are summarized below.
More information about the different modes can be found in Section “18.6. Timing” on page 118.
18.5.1. Internal XRAM Only
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 4 kB boundaries. As an
example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.
18.5.2. Split Mode without Bank Select
When bit EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
EMI0CF[3:2] = 00
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
0xFFFF
0x0000
EMI0CF[3:2] = 01
(No Bank Select)
On-Chip XRAM
Off-Chip
Memory
Figure 18.3. EMIF Operating Modes
0xFFFF
0x0000
Rev. 1.0
EMI0CF[3:2] = 10
On-Chip XRAM
(Bank Select)
Off-Chip
Memory
0xFFFF
0x0000
C8051F70x/71x
EMI0CF[3:2] = 11
Off-Chip
Memory
0xFFFF
0x0000
117
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