C8051F561-IQR Silicon Labs, C8051F561-IQR Datasheet - Page 141
C8051F561-IQR
Manufacturer Part Number
C8051F561-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB CAN2.0 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F561-IQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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Quantity
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Part Number:
C8051F561-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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SFR Definition 16.2. RSTSRC: Reset Source
SFR Address = 0xEF; SFR Page = 0x00
Note: Do not use read-modify-write operations on this register
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
FERROR Flash Error Reset Flag.
C0RSEF Comparator0 Reset Enable
PINRSF
SWRSF
Unused
PORSF
Name
R
7
0
Unused.
and Flag.
Software Reset Force and
Flag.
Enable and Flag.
Power-On/V
Reset Flag, and V
Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
R
6
Description
DD
C0RSEF
Monitor
Varies
R/W
DD
5
monitor
SWRSF
Varies
R/W
Rev. 1.1
Don’t care.
N/A
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Writing a 1 forces a sys-
tem reset.
Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Writing a 1 enables the
V
source.
Writing 1 to this bit
before the V
is enabled and stabilized
may cause a system
reset.
N/A
4
DD
monitor as a reset
WDTRSF
Varies
Write
R
3
DD
C8051F55x/56x/57x
monitor
MCDRSF
Varies
R/W
2
0
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 anytime a power-
on or V
occurs.
When set to 1 all other
RSTSRC flags are inde-
terminate.
Set to 1 if RST pin caused
the last reset.
PORSF
Varies
R/W
DD
1
Read
monitor reset
PINRSF
Varies
R
0
141
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