M24512-WMN6TP STMicroelectronics, M24512-WMN6TP Datasheet
M24512-WMN6TP
Specifications of M24512-WMN6TP
M24512-WMN6TP
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M24512-WMN6TP Summary of contents
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... Features ■ M24512-R/M24512-W: 512 Kbit EEPROM 2 addressed through the I C bus ■ M24512-DR: 512 Kbit EEPROM addressed 2 through the I C bus, with additional Identification page 2 ■ Supports the I C bus modes: – 1 MHz Fast-mode Plus – 400 kHz Fast mode – 100 kHz Standard mode ■ ...
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... Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 Page Write (memory array 3.10 Identification Page Write (M24512-DR only 3.11 Lock Identification Page (M24512-DR only 3.12 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 3.13 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 3.14 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 Random Address Read (in memory array ...
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... M24512-R, M24512-W, M24512-DR 3.18 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.19 Read Identification Page status (locked/unlocked 3.20 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 16459 Rev 19 Contents 3/3 ...
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... List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code (for memory array Table 3. Device select code to access the Identification page (M24512-DR only Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8 ...
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... M24512-R, M24512-W, M24512-DR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO, UFDFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Figure Fast mode (f C bus parasitic capacitance (C 2 Figure Fast mode Plus (f bus parasitic capacitance (C 2 Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Write mode sequences with (data write inhibited Figure 8 ...
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... Description The M24512-x devices are I (EEPROM). They are organized × 8 bits. The M24512-x can decode the type identifier code (1010) in accordance with the I definition. The M24512-DR also decodes the type identifier code (1011) when accessing the identification page. The M24512-DR offers an additional Identification Page (128 bytes) which can be written and (later) permanently locked in Read Only mode ...
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... M24512-R, M24512-W, M24512-DR Figure 2. SO, UFDFPN and TSSOP connections 1. See Package mechanical data SCL SDA section for package dimensions, and how to identify pin-1. Doc ID 16459 Rev 19 Description AI04035e 7/39 ...
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... When Write Control (WC) is driven High, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/39 indicates how the value of the pull-up resistor can be calculated M24xxx M24xxx Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR . (Figure 5 indicates how CC Ai12806 , and IL CC ...
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... M24512-R, M24512-W, M24512-DR 2.5 V ground the reference for the V SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V order to secure a stable DC supply voltage recommended to decouple the V a suitable capacitor (usually of the order 100 nF) close to the V pins ...
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... R bus bus bus must be below the 100 ns time constant line represented on the left. 30 100 Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR value versus bus = 1.3 µs (min value for LOW = 400 kHz), the R bus × C bus V CC SCL I²C bus master ...
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... The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. Device select code to access the Identification page (M24512-DR only) Device select code 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. ...
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... Signal description Table 4. Most significant address byte b15 b14 Table 5. Least significant address byte b7 b6 12/39 b13 b12 b11 Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR b10 ...
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... M24512-R, M24512-W, M24512-DR 3 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Read and write operations can be performed on this page, except if a Lock instruction has been issued to permanently write protect it. The M24512-DR Identification page is addressed in the same way as the memory array, except that the 4-bit device type identifier of the device select code is 1011b (see ...
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... M24512-R, M24512-W, M24512-DR Figure 7. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel Byte addr Byte addr R/W NO ACK NO ACK Data in N Doc ID 16459 Rev 19 ...
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... NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 16/39 M24512-R, M24512-W, M24512-DR , and the successful completion of a Write operation, W Figure Doc ID 16459 Rev 19 ...
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... ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word therefore recommended to write by word (4 bytes) in order to benefit from the larger amount of Write cycles. The M24512-x devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-bytes. Doc ID 16459 Rev 19 ...
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... Device operation Figure 8. Write mode sequences with (data write enabled) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) 18/39 M24512-R, M24512-W, M24512-DR ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel Byte addr Byte addr R/W ACK ...
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... M24512-R, M24512-W, M24512-DR Figure 9. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device 3.13 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t ...
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... Dev sel Data out 1 R/W ACK ACK Dev sel * Byte addr Byte addr R/W ACK NO ACK Data out N Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR ACK ACK NO ACK Dev sel * Data out R/W ACK NO ACK Data out N ACK ACK ACK Dev sel * ...
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... M24512-R, M24512-W, M24512-DR 3.16 Current Address Read (in memory array) For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented ...
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... For all Read instructions, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. 22/39 M24512-R, M24512-W, M24512-DR Doc ID 16459 Rev 19 ...
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... M24512-R, M24512-W, M24512-DR 4 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied ...
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... Input levels Input and output timing reference levels Figure 11. AC test measurement I/O waveform 24/39 Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR Min. Max. Unit 2.5 5.5 –40 85 –40 125 Min. Max. ...
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... E0, E1, E2) V Output low voltage OL 1. The new M24512-W devices (identified by the process letter K) offer I 2. Only for devices operating at the f 3. Characterized value, not tested in production. 4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the ...
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... If the application uses the voltage range R device within 2.5<V to Table 12: DC characteristics (voltage range W) 2. The new M24512-R and M24512-DR devices (identified by the process letter K) offer I 3. Only for devices operating Characterized value, not tested in production. 5. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the ...
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... SCL) required by the SDA bus line to reach either 0.3V CLQV 0.7V , assuming that The current M24xxx devices (identified by the Process letter A) offer t and M24512-DR device (identified by the process letter K) offer t safe margin compared to the 50 ns minimum value recommended by the I Test conditions specified in Table Parameter Clock frequency ...
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... NS 1. Only new M24512-R and M24512-DR devices identified by the process letter K are qualified at 1 MHz. 2. All values are referred There is no min. or max. values for the input signal rise and fall times however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f < ...
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... M24512-R, M24512-W, M24512-DR Figure 12. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDL tXH1XH2 Start condition SCL SDA In tCHDH Stop condition SCL tCLQV SDA Out tCHCL tCLCH tCLDX tDXCH SDA Change SDA Input tW Write cycle tCHCL tCLQX Data valid Data valid Doc ID 16459 Rev 19 ...
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... Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512- 6L_ME (1) inches Typ Min Max 0.0984 0 0.0098 0.0594 0.0787 0.0157 0.0138 0.0201 0.0079 0.0039 0.0138 0.0039 0.2382 ...
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... M24512-R, M24512-W, M24512-DR Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 17. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR c α TSSOP8AM (1) inches Typ Min Max 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 ...
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... M24512-R, M24512-W, M24512-DR Figure 16. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, outline 1. Drawing is not to scale. 2. The central pad (the area the above illustration) is pulled, internally allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process ...
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... Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for device grade 3. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 34/39 M24512-R, M24512-W, M24512-DR M24512– W (1) Doc ID 16459 Rev 19 MW ...
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... M24512-R, M24512-W, M24512-DR Table 21. Available M24512-W and M24512-R products (package, voltage range, temperature grade) Package SO8N (MN) SO8W (MW) TSSOP (DW) UFDFPN8 (MB) WLCSP (CS) Table 22. Available M24512-DR products (package, voltage range, temperature grade) Package SO8N (MN) TSSOP (DW) UFDFPN8 (MB) M24512-W 2 5.5 V Range 6, Range 3 Range 6 Range M24512-DR 1 5.5 V ...
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... Table 12: DC characteristics (voltage range Power On Reset paragraph specified. t max value modified in W added. Plating technology changed in scheme. Resistance and capacitance renamed in Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR Changes (min) improved to –0.45V. IL section and Table 20: Ordering information Table 11: Input parameters = 5.5V added to Table 12: DC characteristics CC ...
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... Note 1 removed from Table 12: DC characteristics (voltage range SO8W package specifications modified in data. Table 23: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) M24512-x products (package, voltage range, temperature grade) Section 2.5: V ground added. Small text changes max changed and ...
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... CLQX CLQV t and t updated in CLQX CLQV Section 8: Part numbering Reference to the SURE program removed in Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new M24512-R and M24256-BR (process letter K). Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR Changes modified. = 400 kHz): maximum R value versus bus C ...
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... Clarified cover page. Section 1: Description inserted paragraph clarifying Identification Page. Section 3.1: Start condition Section 3.7: Write operations Section 3.10: Identification Page Write (M24512-DR only) 19 Section 3.18: Read Identification Page Table 7: Absolute maximum ratings Table 10: AC test measurement conditions Table 12: DC characteristics (voltage range W) ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 40/40 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 16459 Rev 19 M24512-R, M24512-W, M24512-DR ...