M95256-RDW6TP STMicroelectronics, M95256-RDW6TP Datasheet - Page 11

• Manufacturer Part Number: M95256-RDW6TP
• Description: IC EEPROM 256KBIT 2MHZ 8TSSOP
• Manufacturer: STMicroelectronics

Specifications of M95256-RDW6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6352-2

M95256-DR, M95256, M95256-W, M95256-R
3.8.2
3.8.3
4
4.1
Power-up conditions
When the power supply is turned on, V
time, the Chip Select (S) line is not allowed to float but should follow the V
therefore recommended to connect the S line to V
Figure
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The V
defined in
Power-down
During Power-down (continuous decrease of V
operating voltage defined in
●
●
Operating features
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5
with Serial Clock (C) being low.
deselected (Chip Select S should be allowed to follow the voltage applied on V
in Standby Power mode (there should not be an internal Write cycle in progress).
CC
17).
also shows what happens if the rising and falling edges are not timed to coincide
voltage has to rise continuously from 0 V up to the minimum V
Table
8,
Table 9
and
Table
Doc ID 12276 Rev 13
Table 10
8,
Table 9
CC
and the rise time must not vary faster than 1 V/µs.
rises continuously from V
and
CC
Figure
Table
CC
supply voltage below the minimum V
via a suitable pull-up resistor (see
5).
10), the device must be:
SS
to V
CC
Operating features
CC
operating voltage
CC
voltage, it is
. During this
CC
)
11/47
CC