CY7C1021D-10ZSXI Cypress Semiconductor Corp, CY7C1021D-10ZSXI Datasheet - Page 6

• Manufacturer Part Number: CY7C1021D-10ZSXI
• Description: IC SRAM 1MBIT 10NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1021D-10ZSXI

• Memory Size: 1M (64K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 10 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 80 mA
• Organization: 64 K x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Density: 1Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 16b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 80mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1972; CY7C1021D-10ZSXI

Data Retention Characteristics
Data Retention Waveform
Switching Waveforms
Notes
Document #: 38-05462 Rev. *H
V
I
t
t
12. Full device operation requires linear V
13. Device is continuously selected. OE, CE, BHE and/or BLE = V
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Parameter
DATA OUT
CCDR
CDR
R
ADDRESS
CURRENT
DR
BHE, BLE
[12]
DATA OUT
ADDRESS
SUPPLY
[3]
V
CE
OE
CC
V
CE
CC
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CC
for Data Retention
PREVIOUS DATA VALID
HIGH IMPEDANCE
Description
t
t
Figure 3. Read Cycle No. 1 (Address Transition Controlled)
LZCE
PU
CC
ramp from V
t
ACE
Figure 4. Read Cycle No. 2 (OE Controlled)
t
t
LZBE
t
DBE
LZOE
t
DOE
t
50%
OHA
t
CDR
4.5V
(Over the Operating Range)
DR
to V
t
IL
CC(min)
AA
.
V
V
CC
IN
> 50 s or stable at V
t
RC
> V
= V
DATA RETENTION MODE
CC
DR
– 0.3 V or V
= 2.0 V, CE > V
t
RC
RC
V
DR
>
CC(min)
Conditions
2V
IN
DATA VALID
< 0.3 V
> 50 s.
CC
– 0.3 V,
[14, 15]
Industrial
Automotive
[13, 14]
t
DATA VALID
HZOE
4.5V
t
R
t
t
HZCE
HZBE
t
PD
Min
2.0
50%
t
RC
0
IMPEDANCE
CY7C1021D
HIGH
Max
10
3
Page 6 of 12
Unit
mA
mA
ns
ns
I
I
V
CC
SB
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