M27C512-12F1 STMicroelectronics, M27C512-12F1 Datasheet - Page 6

• Manufacturer Part Number: M27C512-12F1
• Description: IC EPROM 512KBIT 120NS 28CDIP
• Manufacturer: STMicroelectronics

Specifications of M27C512-12F1

• Format - Memory: EPROMs
• Memory Type: UV EPROM
• Memory Size: 512K (64K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-CDIP (0.600", 15.24mm) Window
• Capacitance, Input: 6 pF
• Capacitance, Output: 12 pF
• Current, Input, Leakage: ±10 μA (Read)
• Current, Operating: 30 mA (Read)
• Current, Output, Leakage: ±10 μA (Read)
• Current, Supply: 30 mA
• Density: 512K
• Organization: 64K×8
• Package Type: FDIP28W
• Temperature, Operating: 0 to +70 °C
• Temperature, Operating, Maximum: 70 °C
• Temperature, Operating, Minimum: 0 °C
• Time, Access: 120 ns
• Time, Fall: ≤20 ns
• Time, Rise: ≤20 ns
• Voltage, Input, High: 6 V (Read)
• Voltage, Input, High Level: 2 V (Min.)
• Voltage, Input, Low: 0.8 V (Read)
• Voltage, Input, Low Level: -0.3 V (Min.)
• Voltage, Output, High: 4.3 V (Read)
• Voltage, Output, Low: 0.4 V (Read)
• Voltage, Programmable: 11.5 V (Min.)
• Voltage, Supply: 5 V
• Memory Configuration: 64K X 8
• Access Time: 120ns
• Supply Voltage Range: 4.5V To 5V
• Memory Case Style: DIP
• No. Of Pins: 28
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1671-5

Device operation
2.3
2.4
6/22
Two line output control
Because EPROMs are usually used in larger memory arrays, the product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between V
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V
power supply connection point.The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
The lowest possible memory power dissipation,
Complete assurance that output bus contention will not occur.
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
CC
, has three segments that are of interest to
CC
and V
SS
. This should
M27C512