CY7C1355C-133AXC Cypress Semiconductor Corp, CY7C1355C-133AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1355C-133AXC
• Description: IC SRAM 9MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1355C-133AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 512K X 18 / 256K X 36
• Clock Frequency: 133MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1862; CY7C1355C-133AXC

Pin Definitions
Document Number: 38-05539 Rev. *H
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
ZZ
DQ
DQP
MODE
V
V
V
TDO
TDI
0
DD
DDQ
SS
, A
1
2
3
s
A
C
, BW
X
, BW
1
Name
, A
B
D
I/O power supply Power supply for the I/O circuitry.
JTAG serial output
JTAG serial input
Input strap pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst
asynchronous
asynchronous
Power supply
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
clock
I/O-
I/O-
I/O
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/load input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Chip enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
Output enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQP
sequence. When tied to V
Power supply inputs to the core of the device.
Ground for the device.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be left unconnected. This pin is not available on
TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left floating or connected to V
resistor. This pin is not available on TQFP packages.
2
1
1
, and CE
and CE
and CE
[1:0]
3
2
are fed to the two-bit burst counter.
3
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
X
is controlled by BW
DD
or left floating selects interleaved burst sequence.
Description
s
and DQP
X
correspondingly.
X
CY7C1355C, CY7C1357C
are placed in a tri-state condition.The
DD
through a pull-up
s
. During
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