CY7C1382D-167AXC Cypress Semiconductor Corp, CY7C1382D-167AXC Datasheet - Page 2

• Manufacturer Part Number: CY7C1382D-167AXC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1382D-167AXC

• Memory Size: 18M (1M x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.4 ns
• Maximum Clock Frequency: 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 275 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 20b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1632

Logic Block Diagram – CY7C1380D/CY7C1380F
Logic Block Diagram – CY7C1382D/CY7C1382F
Note
Document #: 38-05543 Rev. *F
3. CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE
A0, A1, A
A0, A1, A
MODE
BW
ADSC
ADSC
ADSP
BW
BWE
ADV
BW
BW
BWE
ADV
BW
BW
CLK
GW
CE2
CE3
CLK
GW
CE
OE
CE
CE
CE
OE
ZZ
D
C
ZZ
A
B
B
A
1
1
2
3
CONTROL
SLEEP
WRITE REGISTER
WRITE REGISTER
CONTROL
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
SLEEP
DQ
DQ
ADDRESS
REGISTER
DQ
DQ
DQ
DQ
REGISTER
ENABLE
BYTE
BYTE
C ,
BYTE
B ,
BYTE
D ,
A ,
B,
A,
DQP
DQP
DQP
DQP
REGISTER
DQP
DQP
ENABLE
C
B
D
A
B
A
REGISTER
ADDRESS
COUNTER AND
BURST
LOGIC
PIPELINED
PIPELINED
2
CLR
ENABLE
ENABLE
Q1
COUNTER
2
BURST
LOGIC
AND
A
[1:0]
Q1
Q0
WRITE DRIVER
WRITE DRIVER
WRITE DRIVER
WRITE DRIVER
DQ
DQ
DQ
WRITE DRIVER
DQ
WRITE DRIVER
BYTE
BYTE
BYTE
DQ
DQ
D
C ,
BYTE
B ,
A ,
,DQP
DQP
DQP
DQP
B,
A,
DQP
DQP
C
B
D
A
B
A
[3]
[3]
1
).
(1M x 18)
(512K x 36)
MEMORY
ARRAY
MEMORY
ARRAY
SENSE
AMPS
SENSE
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
REGISTERS
OUTPUT
OUTPUT
OUTPUT
BUFFERS
BUFFERS
E
OUTPUT
REGISTERS
INPUT
INPUT
DQP
DQP
DQP
DQP
D Q s
A
D
B
C
Page 2 of 34
DQs
DQP
DQP
A
B
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