CY7C1370D-200BGXC Cypress Semiconductor Corp, CY7C1370D-200BGXC Datasheet
CY7C1370D-200BGXC
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CY7C1370D-200BGXC Summary of contents
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... Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states ...
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... Logic Block Diagram-CY7C1370D (512K x 36) ADDRESS A0, A1, A REGISTER MODE ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 ADV/LD WRITE REGISTRY AND DATA COHERENCY BW a CONTROL LOGIC READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram-CY7C1372D (1M x 18) ADDRESS A0, A1, A ...
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... Contents Features ............................................................................. 1 Functional Description ..................................................... 1 Selection Guide ................................................................ 1 Logic Block Diagram-CY7C1370D (512K x 36) .............. 2 Logic Block Diagram-CY7C1372D (1M x 18) .................. 2 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 6 Introduction ....................................................................... 7 Functional Overview .................................................... 7 Sleep Mode ................................................................. 8 Truth Table ........................................................................ 9 Partial Write Cycle Description ..................................... 10 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11 Disabling the JTAG Feature ...................................... 11 TAP Controller State Diagram ...
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... V DDQ 11 DQc 12 DQc 13 NC CY7C1370D (512K × 36 DQd 18 DQd DDQ DQd 22 DQd 23 DQd 24 DQd DDQ DQd 28 DQd 29 DQPd 30 Document Number: 38-05555 Rev. *H CY7C1370D, CY7C1372D Figure 1. 100-Pin TQFP NC 1 DQPb DQb 79 DQb DDQ DDQ DQb 75 DQb DQb DQb 8 73 DQb DQb DDQ ...
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... A V DDQ B NC/576M C NC/ DDQ DDQ DDQ NC/144M DDQ DDQ B NC/576M C NC/ DDQ DDQ DDQ NC/144M T NC/72M U V DDQ Document Number: 38-05555 Rev. *H Figure 2. 119-Ball BGA CY7C1370D (512K x 36 ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1372D (1M x 18) ...
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... DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document Number: 38-05555 Rev. *H Figure 3. 165-Ball FBGA CY7C1370D (512K x 36 CEN CLK TDI A1 TDO ...
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... The direction of the pins is [17:0] –DQ are placed in a tristate condition. The outputs are automati controlled DQP is controlled controlled CY7C1370D, CY7C1372D and DQP , BW controls DQ and DQP During write s , DQP is controlled ...
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... SRAM is deselected at clock rise by one of the chip enable signals, its output will tristate following the next clock rise. Burst Read Accesses The CY7C1370D and CY7C1372D have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ...
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... OE. Burst Write Accesses The CY7C1370D/CY7C1372D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs ...
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... Truth Table The Truth Table for CY7C1370D and CY7C1372D follows Address Operation Deselect Cycle None Continue Deselect Cycle None Read Cycle (Begin Burst) External Read Cycle (Continue Burst) Next NOP/Dummy Read (Begin Burst) External Dummy Read (Continue Burst) Next Write Cycle (Begin Burst) ...
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... DQP ) a a Write Byte b – (DQ and DQP ) b b Write Both Bytes Note 8. Table only lists a partial listing of the byte write combinations. Any Combination of BW byte write is active. Document Number: 38-05555 Rev valid Appropriate write will be done based on which X CY7C1370D, CY7C1372D ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370D/CY7C1372D incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1370D/CY7C1372D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...
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... It also places the instruction register between the TDI and TDO balls and allows Document Number: 38-05555 Rev. *H CY7C1370D, CY7C1372D the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state ...
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... TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH DON’ UNDEFINED [9, 10] Over the Operating Range Description / ns CY7C1370D, CY7C1372D TDOV t TDOX Min Max Unit MHz ...
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... DDQ I = 8.0 mA 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1370D, CY7C1372D to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...
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... Bit pre-set HIGH. Document Number: 38-05555 Rev. *H CY7C1370D 000 000 Reserved for version number. 01011001000010101 Reserved for future use. 00000110100 Allows unique identification of SRAM vendor Indicate the presence register. Bit Size (x18 Description CY7C1370D, CY7C1372D Description Bit Size (x36 Page [+] Feedback ...
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... BGA Boundary Scan Order Bit # Ball ID Bit # Document Number: 38-05555 Rev. *H [13, 14] Ball ID Bit # Ball CY7C1370D, CY7C1372D Bit # Ball Internal Page [+] Feedback ...
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... R10 11 R11 12 H11 13 N11 14 M11 15 L11 16 K11 17 J11 18 M10 19 L10 20 K10 21 J10 H10 24 G11 25 F11 26 E11 27 D11 28 G10 29 F10 30 E10 Note 15. Bit preset HIGH Document Number: 38-05555 Rev. *H CY7C1370D, CY7C1372D [13, 15] Bit # Ball ID 31 D10 32 C11 33 A11 34 B11 35 A10 36 B10 C10 ...
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... CYC 5-ns cycle, 200 MHz 6-ns cycle, 167 MHz /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1370D, CY7C1372D Test Description Typ Max* Unit Conditions Logical 25°C 361 394 Single-Bit Upsets Logical 25° ...
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... Figure 4. AC Test Loads and Waveforms R = 317Ω 3.3V V DDQ OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1370D, CY7C1372D Min. Max. Unit 70 mA 135 mA 130 mA 125 119 BGA 165 FBGA Unit Max Max ...
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... V minimum initially, before a Read or Write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ = 2.5V. DDQ CY7C1370D, CY7C1372D –200 –167 Unit Max Min Max ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1370D, CY7C1372D OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t OEHZ t DOH t OELZ WRITE READ WRITE DESELECT D(A5) ...
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... A3 A4 D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE [29, 30] Figure 7. ZZ Mode Timing DDZZ High-Z DON’T CARE CY7C1370D, CY7C1372D [25, 26, 28 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI DESELECT or READ Only Page ...
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... Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1372D-167AXI 200 CY7C1370D-200AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1372D-200AXC CY7C1370D-200BGXC 51-85115 119-ball Ball Grid Array ( 2.4 mm) Pb-Free CY7C1370D-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1370D-200AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free 250 CY7C1370D-250AXC 51-85050 100-pin Thin Quad Flat Pack ( ...
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... Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) Document Number: 38-05555 Rev. *H CY7C1370D, CY7C1372D 51-85050 *C Page [+] Feedback ...
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... Document Number: 38-05555 Rev. *H Figure 9. 119-Ball BGA ( 2.4 mm) CY7C1370D, CY7C1372D 51-85115*C Page [+] Feedback ...
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... Document Number: 38-05555 Rev. *H Figure 10. 165-Ball FBGA ( 1.4 mm) CY7C1370D, CY7C1372D 51-85180 *C Page [+] Feedback ...
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... Document History Page Document Title: CY7C1372D/CY7C1370D 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05555 Submission REV. ECN No. Date ** 254509 See ECN *A 276690 See ECN *B 288531 See ECN *C 326078 See ECN *D 370734 See ECN *E 416321 See ECN ...
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... Document Number: 38-05555 Rev. *H ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 21, 2010 CY7C1370D, CY7C1372D PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...