CY7C1514V18-200BZXI Cypress Semiconductor Corp, CY7C1514V18-200BZXI Datasheet - Page 25

• Manufacturer Part Number: CY7C1514V18-200BZXI
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1514V18-200BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document History Page
Document #: 38-05489 Rev. *G
Revision
Document Title: CY7C1512V18/CY7C1514V18, 72 Mbit QDR
Document Number: 38-05489
*A
*B
*C
*D
**
201260
257089
319496
403231
467290
ECN
Orig. Of
Change
NXR
NXR
NJY
NJY
SYT
Submission
See ECN
See ECN
See ECN
See ECN
See ECN
Date
Description Of Change
New Datasheet
Removed foot note 13 on page 12
Modified JTAG ID register definition table on page 21
Changed Max value of t
Max value of t
Changed Max value of t
Max value of t
Included thermal values
Modified capacitance values table: included capacitance values for x8, x18 and
x36 options
Removed CY7C1525V18 from the title
Included 300 MHz Speed bin
Added footnote #1 and accordingly edited the V
Pin Definitions table.
Added Industrial Temperature Grade
Replaced TBDs for I
speed grades
Changed the C
Table
Removed the capacitance value column for the x9 option from Capacitance Table
Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRISTATE
on Page 18
Added Pb-free product information
Updated the Ordering Information by Shading and Unshading MPNs as per avail-
ability
Converted from Preliminary to Final
Added CY7C1525V18 to the title
Removed 300 MHz Speed bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed C/C Pin Description in the features section and Pin Description
Added power up sequence details and waveforms
Added foot notes # 14, 15, 16 on page# 19
Replaced Three-state with Tristate
Changed the description of I
on page# 20, Modified the I
Modified test condition in Footnote # 21 on page# 20 from V
V
Replaced Package Name column with Package Diagram in the Ordering
Information table, Updated the Ordering Information.
Modified the ZQ Definition from Alternately, this pin can be connected directly to
V
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Changed t
changed t
t
Characteristics table. Modified power up waveform
Added additional notes in the AC parameter section
Changed the t
from 0.6 ns to 0.4 ns for 200 MHz, and from 0.7 ns to 0.5 ns for 167 MHz.
Modified AC Switching Waveform, Corrected the typo In the AC Switching Charac-
teristics Table, Updated the Ordering Information Table
CH
DD
DD
from 10 ns to 5 ns and changed t
to Alternately, this pin can be connected directly to V
TH
TCYC
and t
cyc
KHCH
SC
®
IN
from 100 ns to 50 ns, changed t
II SRAM Two Word Burst Architecture
at 200 MHz from 6.3 ns to 7.9 ns.
from 5 pF to 5.5 pF and C
and t
TL
at 167 MHz from 2.8 ns to 2.7 ns
DD
from 40 ns to 20 ns, changed t
HC
and I
cyc
KHCH
value from 0.5 ns to 0.35 ns for 250 MHz,
at 250 MHz from 5.25 ns to 6.3 ns and
DD
X
SB1
at 200 MHz from 2.3 ns to 2.2 ns and
from Input Load Current to Input Leakage Current
and I
for 300 MHz, 250 MHz, 200 MHz and 167 MHz
TDOV
SB
current values
from 20 ns to 10 ns in TAP AC Switching
O
from 7 pF to 8 pF in the Capacitance
SS
TF
/144M And V
from 10 MHz to 20 MHz,
TMSS
DDQ
, t
Relative to GND
DDQ
CY7C1512V18
CY7C1514V18
TDIS
DDQ
DDQ
, t
SS
< V
CS
to V
/288M on the
, t
Page 25 of 26
DD
TMSH
DD
to V
, t
DDQ
TDIH
<
,
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