25LC512-I/SM Microchip Technology, 25LC512-I/SM Datasheet - Page 11
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25LC512-I/SM
Manufacturer Part Number
25LC512-I/SM
Description
IC EEPROM 512KBIT 20MHZ 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.25LC512-ISM.pdf
(36 pages)
Specifications of 25LC512-I/SM
Memory Size
512K (64K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
20MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Memory Configuration
64K X 8
Ic Interface Type
SPI
Clock Frequency
20MHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
SOIJ
No. Of Pins
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
25LC512-I/SM
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
25LC512-I/SM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.4
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25LC512 is busy with a write operation. When set to a
‘
in progress. This bit is read-only.
FIGURE 2-6:
2010 Microchip Technology Inc.
1
W/R = writable/readable. R = read-only.
WPEN
SCK
’, a write is in progress, when set to a ‘
W/R
CS
SO
7
SI
Read Status Register Instruction
(RDSR)
6
–
X
0
X
5
–
0
STATUS REGISTER
X
4
–
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
1
High-Impedance
W/R
BP1
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
0
4
R
1
’, no write is
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS Register
10
5
11
4
12
3
13
2
25LC512
14
1
DS22065C-page 11
15
0