AT89LP828-AU Atmel, AT89LP828-AU Datasheet - Page 95
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AT89LP828-AU
Manufacturer Part Number
AT89LP828-AU
Description
8-bit Microcontrollers - MCU Single-Cycle 8051 8K ISP Flash, 2.4-5.5V
Manufacturer
Atmel
Datasheet
1.AT89LP828-AU.pdf
(149 pages)
Specifications of AT89LP828-AU
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
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17.3
Table 17-1.
Notes:
3654A–MICRO–8/09
MOSI
MISO
SCK
Pin
Pin Configuration
1. In these modes MOSI is active only during transfers. MOSI will be pulled high between transfers to allow other masters to
2. In Push-pull mode MOSI is active only during transfers, otherwise it is tristated to prevent line contention. A weak external
control the line.
pull-up may be required to prevent MOSI from floating.
Mode
Quasi-bidirectional
Push-pull Output
Input-only
Open-drain Output
Quasi-bidirectional
Push-pull Output
Input-only
Open-drain Output
Quasi-bidirectional
Push-pull Output
Input-only
Open-drain Output
SPI Pin Configuration and Behavior when SPE = 1
When the SPI is enabled (SPE = 1), the data direction of the MOSI, MISO, SCK, and SS pins is
automatically overridden according to the MSTR bit as shown in
need to reconfigure the pins when switching from master to slave or vice-versa. For more details
on port configuration, refer to
.
Master (MSTR = 1)
Output
Output
No output (Tristated)
Output
Output
Output
No output (Tristated)
Output
Input (Internal Pull-up)
Input (Tristate)
Input (Tristate)
Input (External Pull-up)
(1)
(2)
(1)
“Port Configuration” on page
Slave (MSTR = 0)
Input (Internal Pull-up)
Input (Tristate)
Input (Tristate)
Input (External Pull-up)
Input (Internal Pull-up)
Input (Tristate)
Input (Tristate)
Input (External Pull-up)
Output (SS = 0)
Internal Pull-up (SS = 1 or DISSO = 1)
Output (SS = 0)
Tristated (SS = 1 or DISSO = 1)
No output (Tristated)
Output (SS = 0)
External Pull-up (SS = 1 or DISSO = 1)
35.
AT89LP428/828
Table
17-1. The user doesn’t
95
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