CY7C037-15AC Cypress Semiconductor Corp, CY7C037-15AC Datasheet
CY7C037-15AC
Specifications of CY7C037-15AC
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CY7C037-15AC Summary of contents
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... True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 32K x 16 organization (CY7C027) • 64K x 16 organization (CY7C028) • 32K x 18 organization (CY7C037) • 64K x 18 organization (CY7C038) • 0.35-micron CMOS for optimum speed/power [1] • High-speed access: 12 /15/20 ns • ...
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... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View) ...
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... Selection Guide Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) (Both ports TTL level) SB1 Typical Standby Current for I (mA) (Both ports CMOS level) SB3 Note: 7. This pin is NC for CY7C037. Document #: 38-06042 Rev. *A 100-Pin TQFP (Top View ...
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... Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect Input Voltage Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial CY7C027/028 CY7C037/038 Description V and –A for 64K devices –I/O for x16 devices; I/O – ...
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... Ind. Com’l. 125 205 , [10] IH Ind. Com’l. 0.05 0.5 & [10] Ind. Com’l. 115 185 [10] Ind. CY7C027/028 CY7C037/038 CY7C027/028 CY7C037/038 -15 -20 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.2 2.2 0.8 –10 10 –10 190 280 180 305 50 70 ...
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... ALL INPUT PULSES 3.0V 90% 10% GND 3 ns [13] 1.00 0.90 0.80 0.70 = 1.4V 0.60 TH 0.50 0.40 0.30 0.20 0.10 0. CY7C027/028 CY7C037/038 Max OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for CKLZ OLZ including scope and jig) 90% 10 Capacitance (pF) (b) Load Derating Curve ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document #: 38-06042 Rev. *A [14] CY7C027/028 CY7C037/038 [1] -12 -15 Min. Max. Min. Max less than t and t is less than t HZCE LZCE HZOE LZOE CY7C027/028 CY7C037/038 -20 Min. Max. Unit time. SCE . Page ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C027/028 and CY7C037/038 are designed with bat- tery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...
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... To access RAM SEM = Document #: 38-06042 Rev. *A [23 ,24, 25 [23, 26, 27] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads access semaphore SEM = CY7C027/028 CY7C037/038 t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE . IL Page ...
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... Document #: 38-06042 Rev. *A [28, 29, 30, 31 [31] t PWE [34] t HZWE t SD [28, 29, 30, 34, 35 SCE LOW CE or SEM and a LOW UB or LB. PWE PWE , SEM = CY7C027/028 CY7C037/038 [34] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD . PWE Page ...
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... SPS Document #: 38-06042 Rev. *A [37 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [38, 39, 40] MATCH t SPS MATCH = CE = HIGH CY7C027/028 CY7C037/038 t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW Document #: 38-06042 Rev. *A [41 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C027/028 CY7C037/038 BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06042 Rev. *A [42] ADDRESS MATCH BLC ADDRESS MATCH BLC [42 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C027/028 CY7C037/038 t BHC t BHC Page ...
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... Notes: 43. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06042 Rev [43 [44] t INR t WC [43 [44] [44] t INR ) is deasserted first R asserted last CY7C027/028 CY7C037/038 t RC READ 7FFF (FFFF for CY7C028/38 READ 7FFE (FFFE for CY7C028/38) Page ...
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... Architecture The CY7C027/028 and CY7C037/038 consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C027/028 CY7C037/038 I/O –I/O Operation 0 8 High Z Deselected: Power-Down High Z Deselected: Power-Down High Z Write to Upper Byte Only Data In Write to Lower Byte Only ...
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... Speed (ns) Ordering Code [1] 12 CY7C028-12AC 15 CY7C028-15AC 20 CY7C028-20AC CY7C028-20AI 32K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C037-12AC 15 CY7C037-15AC 20 CY7C037-20AC 64K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C038-12AC 15 CY7C038-15AC 20 CY7C038-20AC CY7C038-20AI Document #: 38-06042 Rev. *A Package Name Package Type A100 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C027/028 CY7C037/038 51-85048-A Page ...
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... Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Document Number: 38-06042 Issue REV. ECN NO. Date ** 110190 09/29/01 *A 122292 12/27/02 Document #: 38-06042 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00666 to 38-06042 RBI Power up requirements added to Maximum Ratings Information ...