C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 107
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
- Current page: 107 of 220
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11.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
occurs before the device is released from reset. The V
Table 2.8, “Reset Electrical Characteristics,” on page 32. Figure 11.2 plots the power-on and V
reset timing.
Note: Please refer to Section “20.4. VDD Monitors and VDD Ramp Time” on page 211 for definition of
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. Both the V
and VDDMON1) are enabled following a power-on reset.
Note: Please refer to Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for
RST
. V
ramp time in older silicon revisions A and B.
recommendations related to minimum V
DD
Logic H IG H
Logic LO W
ramp time is defined as how fast V
1.0
V
R ST
/RST
Figure 11.2. Power-On and V
P ow er-O n
R eset
DD
T
.
P O R D e lay
DD
Rev. 1.4
ramps from 0 V to V
DD
RST
Monitor Reset Timing
threshold and T
RST
M onitor
C8051F52x/F53x
R eset
V D D
. An additional delay (T
PORDelay
DD
monitors (VDDMON0
DD
are specified in
VDD
V
settles above
RST
DD
PORDelay
and V
monitor
t
107
DD
)
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