C8051F531-ITR Silicon Labs, C8051F531-ITR Datasheet - Page 77
C8051F531-ITR
Manufacturer Part Number
C8051F531-ITR
Description
8-bit Microcontrollers - MCU 8KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F531-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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less than 100 nA. See Section “13.1. Priority Crossbar Decoder” on page 122 for details on configuring
Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0.25 V to
(V
in Table 2.7 on page 31.
The Comparator response time may be configured in software via the CPTnMD register (see SFR Defini-
tion 7.3). Selecting a longer response time reduces the Comparator supply current. See Table 2.7 on
page 31 for complete timing and current consumption specifications.
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Table 2.7 on page 31, settings of 20, 10 or 5 mV of negative hysteresis can
be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis
is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “10. Interrupt Handler” on page 98). The CP0FIF flag is set to
logic 1 upon a Comparator falling-edge detect, and the CP0RIF flag is set to logic 1 upon the Comparator
rising-edge detect. Once set, these bits remain set until cleared by software. The output state of the Com-
parator can be obtained at any time by reading the CP0OUT bit. The Comparator is enabled by setting the
CP0EN bit to logic 1 and is disabled by clearing this bit to logic 0. When the Comparator is enabled, the
internal oscillator is awakened from SUSPEND mode if the Comparator output is logic 0.
REGIN
) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given
(Programmed with CP0HYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CP0-
VIN+
CP0+
VIN-
V
Disabled
OL
Figure 7.2. Comparator Hysteresis Plot
V
OH
+
_
CP0
Positive Hysteresis
Maximum
OUT
Rev. 1.4
Negative Hysteresis
Disabled
Negative Hysteresis
C8051F52x/F53x
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
77
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