CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 19

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 001-06984 Rev. *B
Power-up Waveforms
Power-up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
Notes:
14. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
• Apply power with DOFF tied HIGH (All other inputs can be
• Provide stable power and clock (K, K) for 1024 cycles to
V
HIGH or LOW)
— Apply V
— Apply V
lock the DLL.
DD
/
DOFF
V
DDQ
K
K
DD
DDQ
before V
before V
DDQ
REF
Unstable Clock
Clock Start (Clock Starts after
or at the same time as V
V
DD
[14]
/
V
PRELIMINARY
DDQ
REF
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
DDQ
• DLL uses K clock as its synchronizing input. The input
• The DLL will function at frequencies down to 80 MHz.
• If the input clock is unstable and the DLL is enabled, then
Fix High (or tied to V DDQ )
should have low phase jitter, which is specified as t
the DLL may lock onto an incorrect frequency, causing
unstable SRAM behavior. To avoid this, provide 1024 cycles
stable clock to relock to the desired clock frequency
> 1024 Stable clock
Stable)
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Operation
Page 19 of 26
KC Var
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