CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 21

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 001-06984 Rev. *B
AC Test Loads and Waveforms
Thermal Resistance
Switching Characteristics
t
t
t
t
t
t
Set-up Times
t
t
t
t
Notes:
22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
24. This part has a voltage regulator internally; t
25. For D0 data signal on CY7C1525AV18 device, t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
Parameter
Parameter
[26]
pulse levels of 0.25V to 1.25V, and output loading of the specified I
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
can be initiated.
Cypress
OUTPUT
Device
Under
Test
Θ
Θ
JC
JA
V
REF
ZQ
(a)
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
t
t
t
t
t
t
t
t
t
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
Consortium
Z
Parameter
RQ =
250Ω
0.75V
0
= 50Ω
[21]
Description
V
REF
V
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising
edge to rising edge)
Address Set-up to K Clock Rise
Control Set-up to K Clock Rise (LD, R/W)
Double Data Rate Control Set-up to Clock
(K/K) Rise (BWS
D
DD
Over the Operating Range
[X:0]
R
L
= 0.75V
(Typical) to the first Access
= 50Ω
POWER
Set-up to Clock (K/K) Rise
SD
is 0.5ns for 200MHz, and 250MHz frequencies.
is the time that the power needs to be supplied above V
INCLUDING
Device
Under
Test
OUTPUT
JIG AND
SCOPE
Description
V
0
REF
, BWS
PRELIMINARY
ZQ
OL
1
/I
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/ JESD51.
, BWS
OH
0.75V
RQ =
250Ω
(b)
and load capacitance shown in (a) of AC Test Loads.
[22, 23]
V
[24]
REF
2
, BWS
= 0.75V
Test Conditions
R = 50Ω
5 pF
3
)
Min. Max
0.35
0.35
0.35
0.35
4.0
1.6
1.6
1.8
250 MHz
0.25V
1
0
6.3
1.8
DD
–
–
–
–
–
–
–
minimum initially before a read or write operation
1.25V
REF
Min.
5.0
2.0
2.0
2.2
0.4
0.4
0.4
0.4
200 MHz
1
0
Slew Rate = 2 V/ns
= 0.75V, RQ = 250Ω, V
ALL INPUT PULSES
0.75V
165 FBGA Package
Max Min. Max
7.9
2.2
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
–
–
–
–
–
–
–
16.2
6.0
2.4
2.4
2.7
0.5
0.5
0.5
0.5
2.3
167 MHz
1
0
Page 21 of 26
8.4
2.7
DDQ
–
–
–
–
–
–
–
[22]
= 1.5V, input
Unit
°C/W
°C/W
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
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