VRS51C1100-40-Q Cypress Semiconductor, VRS51C1100-40-Q Datasheet - Page 24

• Manufacturer Part Number: VRS51C1100-40-Q
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

UART Transmission in Mode 0
Any instruction that uses SBUF as a destination
register may initiate a transmission. The “write to
SBUF” signal also loads a 1 into the 9
transmit shift register and informs the TX control block
to begin a transmission. The internal timing is such that
one full machine cycle will elapse between a write to
SBUF instruction and the activation of SEND.
The SEND signal enables the output of the shift
register to the alternate output function line of P3.0 and
enables SHIFT CLOCK to the alternate output function
line of P3.1.
At every machine cycle in which SEND is active, the
contents of the transmit shift register are shifted to the
right by one position.
Zeros come in from the left as data bits shift out to the
right. The TX control block sends its final shift and
deactivates SEND while setting T1 after one condition
is fulfilled: When the MSB of the data byte is at the
output position of the shift register; the 1 that was
initially loaded into the 9
the MSB; and all positions to the left of that contain
zeros. Once these conditions are met, the deactivation
of SEND and the setting of T1 occur at T1 of the 10
machine cycle after the “write to SBUF” pulse.
UART Reception in Mode 0
When REN and R1 are set to 1 and 0, respectively,
reception is initiated. The bits 11111110 are written to
the receive shift register at the end of the next machine
cycle by the RX control unit. In the following phase, the
RX control unit will activate RECEIVE.
The contents of the receive shift register are shifted
one position to the left at the end of every machine
cycle during which RECEIVE is active. The value that
comes in from the right is the value that was sampled
at the P3.0 pin.
1’s are shifted out to the left as data bits are shifted in
from the right. The RX control block is flagged to do
one last shift and load the SBUF when the 0 that was
initially loaded into the rightmost position arrives at the
leftmost position in the shift register.
______________________________________________________________________________________________
www.ramtron.com
VRS51C1100
th
position is just to the left of
th
position of the
th
UART Operation in Mode 1
In a Mode 1 operation, 10 bits are transmitted (through
TXD) or received (through RXD). The transactions are
composed of: a Start bit (Low); 8 data bits (LSB first)
and a Stop bit (high). The reception is completed once
the Stop bit sets the RB8 flag in the SCON register.
Either Timer 1 or Timer 2 controls the baud rate in this
mode.
The following diagram demonstrates the serial port
structure when configured in Mode 1.
F
SMOD
IGURE
RCLK
Timer 1
Overflow
÷2
0 1
18: S
Write to
0
0
SBUF
Timer 2
Overflow
1
1
RXD
ERIAL
TCLK
1-0 Transition
Detector
P
ORT
÷16
1
M
D
S
ODE
CLK
Start
Detector
LOAD SBUF
Start
TX Clock
÷16
Bit
1
Q
AND
RX Clock
3 B
ZERO DETECTOR
TX Control Unit
LOCK
RX Control Unit
Internal Bus
TI
RI
Internal Bus
D
SBUF
SBUF
9-Bit Shift Register
IAGRAM
Shift
Serial Port
Interrupt
Shift
Send
Data
SHIFT
READ SBUF
SBUF
Load
page 24 of 50
TXD