VRS51C1100-40-Q Cypress Semiconductor, VRS51C1100-40-Q Datasheet - Page 6

• Manufacturer Part Number: VRS51C1100-40-Q
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

VRS51C1100 Program + Data Flash
Memory
The VRS51C1100 includes 64KB of on-chip Flash
memory that can be used as program memory or as
non-volatile data storage memory using the In-
Application
VRS51C1100 also includes 64KB of data storage
Flash memory that is also IAP programmable.
ISP Boot Program Memory Zone
The upper portion of the VRS51C1100 Flash program
memory can be reserved to store an ISP (In-System
Programmable) boot loader program.
This boot program can be used to program the Flash
memory via the serial interface (or via any other
method). by making use of the In-Application
Programming (IAP) feature. This allows the processor
to load the program or data from an external device or
system, and to program it into the Flash memory (see
the VRS51C1100 IAP feature section).
The size of the memory block reserved for the ISP
boot loader program (when activated) is adjustable
from 512 to 4KB bytes in increments of 512 bytes,
using the ISP Page config parameter.
F
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www.ramtron.com
ISP Program Size =
ISP Page Config value x 512Bytes
IGURE
VRS51C1100
3: VRS51C1100-ISP P
Programming
ROGRAM SIZE VS
ISP C
feature
ONFIG
. V
ALUE
(IAP).
The
FFFFh
FE00h
FC00h
FA00h
F800h
F600h
F400h
F200h
F000h
0000h
Programming the ISP Boot Program
The ISP boot program is programmed into the device
using a parallel programmer, such as the VERSAMCU-
PPR, or a commercial parallel programmer that
supports the VRS51C1100. The Flash memory
reserved for the ISP program is defined by the parallel
programmer software (ISP Page Config) when the
device is programmed.
When programming the ISP boot program into the
VRS51C1100, the “lock bit” option should be activated
to protect the ISP Flash memory zone from being
inadvertently erased, which can happen when Flash
Erase operations are performed under the control of
the ISP boot program, or to prevent the VRS51C1100
Flash memory from being read back using a parallel
programmer.
If an Erase operation is performed using a parallel
programmer, the entire Flash memory, including the
ISP Boot program memory zone, will be erased.
ISP Boot Program Start Conditions
Setting the ISP page configuration to a value other
than 0 will cause the processor to jump to the base
address of the ISP boot code when a hardware reset is
performed (provided that the value FFh is present at
program address 0000h).
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