AT24HC02B-PU Atmel, AT24HC02B-PU Datasheet - Page 6

• Manufacturer Part Number: AT24HC02B-PU
• Description: IC EEPROM 2KBIT 1MHZ 8DIP
• Manufacturer: Atmel

Specifications of AT24HC02B-PU

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 256 x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Memory Configuration: 256 X 8
• Clock Frequency: 1MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT24HC02B-10PU-1.8; AT24HC02B-10PU-1.8

5. Device Operation
6
AT24HC02B
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see
Data changes during SCL high periods will indicate a start or stop condition as defined below.
Figure 5-1.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must
precede any other command (see
Figure 5-2.
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see
ure
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words.
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24HC02B features a low-power standby mode that is enabled: (a)
upon power-up and (b) after the receipt of the Stop bit and the completion of any internal
operations.
5-2).
SDA
SCL
SDA
SCL
Data Validity
Start and Stop Definition
START
.
The EEPROM sends a “0” to acknowledge that it has received each
DATA STABLE
Figure
5-2).
CHANGE
DATA
DATA STABLE
STOP
5134E–SEEPR–3/08
Figure
5-1).
Fig-