AT24HC02BN-SH-T Atmel, AT24HC02BN-SH-T Datasheet - Page 6

• Manufacturer Part Number: AT24HC02BN-SH-T
• Description: IC EEPROM 2KBIT 1MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT24HC02BN-SH-T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 2Kb
• Interface Type: Serial (2-Wire)
• Organization: 256x8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT24HC02BN-10SU-1.8 SL383; AT24HC02BN-10SU-1.8 SL383

5. Device Operation
Figure 5-1.
6
SCL
SDA
AT24HC02B/04B
Software Reset Protocol
Start Bit
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see to
7). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see to
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see
ure 7-3 on page
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24HC02B/04B features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any two-wire
part can be protocol reset by following these steps (a) Create a start bit condition. (b) Clock nine
cycles. (c) Create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
1
8).
2
Dummy Clock Cycles
3
Figure 7-3 on page
8
9
8).
Start Bit
Figure 7-2 on page
Stop Bit
5192C–SEEPR–01/09
Fig-