C8051F315R Silicon Labs, C8051F315R Datasheet - Page 70
C8051F315R
Manufacturer Part Number
C8051F315R
Description
8-bit Microcontrollers - MCU 8KB 10ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F313R.pdf
(228 pages)
Specifications of C8051F315R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
1.25 KB
On-chip Adc
No
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
QFN-28
Mounting Style
SMD/SMT
Data Rom Size
128 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
25
Number Of Timers
5
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
1500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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C8051F310/1/2/3/4/5/6/7
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and its supply current falls to less than 100 nA. See
page 131
externally driven from –0.25 V to (V
trical specifications are given in Table 7.1.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current.
See Table 7.1 for complete timing and current consumption specifications.
70
CMX1N1
CMX1N0
CMX1P1
CMX1P0
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
P1.2
P1.6
P2.2
P2.6
P1.3
P1.7
P2.3
P2.7
Figure 7.2. Comparator1 Functional Block Diagram
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1OUT
CP1RIF
CP1FIF
CP1EN
DD
) + 0.25 V without damage or upset. The complete Comparator elec-
CP1 +
CP1 -
CP1MD1
CP1MD0
CP1RIE
CP1FIE
Rev. 1.7
+
-
GND
VDD
Section “13.1. Priority Crossbar Decoder” on
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Rising-edge
CP1
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP1
CP1A
CP1
CP1
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