C8051F312R Silicon Labs, C8051F312R Datasheet - Page 106
C8051F312R
Manufacturer Part Number
C8051F312R
Description
8-bit Microcontrollers - MCU 8KB 10ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F313R.pdf
(228 pages)
Specifications of C8051F312R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
1.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
LQFP-32
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
21
Data Rom Size
128 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
29
Number Of Timers
5
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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C8051F310/1/2/3/4/5/6/7
9.1.
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
ramp time increases (V
the power-on and V
delay (T
Note: The maximum V
reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
9.2.
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
106
RST
. An additional delay occurs before the device is released from reset; the delay decreases as the V
Power-On Reset
PORDelay
Power-Fail Reset / V
DD
) is typically less than 0.3 ms.
Logic HIGH
Logic LOW
reaches the V
RST
Figure 9.2. Power-On and V
DD
2.70
2.55
2.0
1.0
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
ramp time is 1 ms; slower ramp times may cause the device to be released from
ramp time is defined as how fast V
/RST
RST
V
RST
DD
level.
Monitor
Power-On
Reset
T
PORDelay
Rev. 1.7
DD
Monitor Reset Timing
DD
DD
ramps from 0 V to V
to drop below V
Monitor
Reset
VDD
DD
monitor is disabled following a
RST
RST
VDD
, the power supply
). Figure 9.2. plots
DD
DD
t
dropped below
settles above
DD
returns
DD
DD
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