ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 30

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

ST72E311 ST72T311
I/O PORTS (Cont’d)
5.1.4 Register Description
5.1.4.1 Data registers
Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Port D Data Register (PDDR)
Port E Data Register (PEDR)
Port F Data Register (PFDR)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D7-D0 Data Register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
5.1.4.2 Data direction registers
Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
Port C Data Direction Register (PCDDR)
Port D Data Direction Register (PDDDR)
Port E Data Direction Register (PEDDR)
Port F Data Direction Register (PFDDR)
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
Bit 7:0 = DD7-DD0 Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
30/101
DD7
D7
7
7
30
DD6
D6
DD5
D5
DD4
D4
DD3
D3
DD2
D2
DD1
D1
DD0
D0
0
0
5.1.4.3 Option registers
Port A Option Register (PAOR)
Port B Option Register (PBOR)
Port C Option Register (PBOR)
Port D Option Register (PBOR)
Port E Option Register (PBOR)
Port F Option Register (PFOR)
Read/Write
Reset Value: see Register Memory Map
Bit 7:0 = O7-O0 Option Register 8 bits.
The OR register allow to distinguish in input mode
if the interrupt capability or the floating configura-
tion is selected.
In output mode it select push-pull or open-drain
capability.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: input pull-up with interrupt
Output mode:
0: open-drain configuration
1: push-pull configuration
O7
7
O6
O5
O4
O3
O2
O1
Table 4
O0
0