ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 67

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4 Functional Description
Figure 1
(SPI) block diagram.
This interface contains 3 dedicated registers:
Refer to the CR, SR and DR registers in
0.1.7
5.5.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
– Select the SPR0 & SPR1 bits to define the se-
– Select the CPOL and CPHA bits to define one
– The SS pin must be connected to a high level
– The MSTR and SPE bits must be set (they re-
rial clock baud rate (see CR register).
of the four relationships between the data
transfer and the serial clock (see
signal during the complete byte transmit se-
quence.
main set only if the SS pin is connected to a
high level signal).
for the bit definitions.
shows the serial peripheral interface
Figure
Section
4).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
is set
and the I bit in the CCR register is cleared.
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