EV-ADF4002SD1Z Analog Devices, EV-ADF4002SD1Z Datasheet - Page 4

• Manufacturer Part Number: EV-ADF4002SD1Z
• Description: Clock & Timer Development Tools PLL EB (No filter or VCO)
• Manufacturer: Analog Devices
• Type: PLL Synthesizers / Multipliers / Dividersr

Specifications of EV-ADF4002SD1Z

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADF4002
• Frequency: 400 MHz
• Operating Supply Voltage: 6 V to 12 V
• Interface Type: USB
• Operating Supply Current: 5 mA
• Factory Pack Quantity: 1
• For Use With: EVAL-SDP-CS1Z

EVALUATION BOARD HARDWARE
The evaluation board requires the use of an SDP-S motherboard
to program the device. This is not included and must be
purchased separately. The
shown in Figure 21, Figure 22, and Figure 23.
POWER SUPPLIES
The board is powered from external banana connectors. The
voltage can vary between 6 V and 12 V. The power supply
circuit provides 3.0 V to the
to choose either 3.0 V or 5 V for the
settings are 3.0 V for the
V
the device.
External power supplies can be used to directly drive the device.
In this case, the user must insert SMA connectors as shown in
Figure 2.
INPUT SIGNALS
The necessary reference input can be sourced from an external
generator. A low noise, high slew rate reference source is best
for achieving the stated performance of the ADF4002. This
reference source can be connected to Connector J11. If
preferred, the edge mount connector, J5, can be inserted and
used instead. A third option is to solder a footprint-compatible
TCXO to Footprint Y2. To use this option, connect 0 Ω links to
R16 and R14.
Digital SPI signals are supplied through the SDP connector, J1.
Using the SDP-S platform is recommended. The SDP_B can
also be used, but Resistor R57 must be removed on the SDP-B
board. Some additional spurious low frequencies may appear if
the SDP-B connector is used.
UG-108
P
. Note that V
DD
should never exceed 3.3 V. This can damage
ADF4002
EV-ADF4002SD1Z
ADF4002
V
DD
ADF4002
and 5 V for the
V
DD
and allows the user
schematics are
V
P
. The default
ADF4002
Rev. A | Page 4 of 24
OUTPUT SIGNALS
All components necessary for LO generation can be inserted on
board. The PLL is made up of the
passive loop filter, and the VCO. The package containing the
VCO must be a T-package (or similar). A low-pass filter must
be inserted between the charge pump output and the VCO
input. In this case, the user must insert the relevant parts as
shown in Figure 2. The VCO output is available at RFOUT
through a standard SMA connector, J2. The MUXOUT signal
can be monitored at Test Point T8 or at SMA Connector J3.
Figure 2. Evaluation Board Silkscreen
Evaluation Board User Guide
ADF4002
synthesizer, a