UPMU-M3L1X-B-EK Silicon Labs, UPMU-M3L1X-B-EK Datasheet - Page 39
UPMU-M3L1X-B-EK
Manufacturer Part Number
UPMU-M3L1X-B-EK
Description
Daughter Cards & OEM Boards UDP SiM3L1xx MCU Card (no LCD)
Manufacturer
Silicon Labs
Datasheet
1.UPMU-M3L1X-B-EK.pdf
(95 pages)
Specifications of UPMU-M3L1X-B-EK
Product
MCU Cards
Core
ARM Cortex M3
Data Bus Width
32 bit
Description/function
MCU Card (No LCD) to use with UDP Motherboard
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Tool Is For Evaluation Of
SiM3L1xx
For Use With
SiM3L1xx
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4.3. Clocking
The SiM3L1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is
derived from one of seven sources: the RTC timer clock (RTC0TCLK), the Low Frequency Oscillator, the Low
Power Oscillator, the divided Low Power Oscillator, the External Oscillator, the PLL0 Oscillator, and the VIORFCLK
pin input. In addition, a divider for the AHB clock provides flexible clock options for the device. The APB clock
services data peripherals and is synchronized with the AHB clock. The APB clock can be equal to the AHB clock or
set to the AHB clock divided by two.
The Clock Control module on SiM3L1xx devices allows the AHB and APB clocks to be turned off to unused
peripherals to save system power. Any registers in a peripheral with disabled clocks will be unable to be accessed
until the clocks are enabled. Most peripherals have clocks off by default after a power-on reset.
RTC0TCLK
VIORFCLK
Oscillator
Oscillator
LFOSC0
LPOSC0
External
PLL0
Figure 4.3. SiM3L1xx Clocking
AHB Clock
APB Clock
Divider
Divider
Clock Control
Rev 0.5
APB clock
Flash Controller
PBCFG and
PB0/1/2/3/4
Registers
AHB clock
USART0
UART0
SPI0
SiM3L1xx
DTM0
Flash
RAM
DMA
39
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