ADP1048DC1-EVALZ Analog Devices, ADP1048DC1-EVALZ Datasheet - Page 68

• Manufacturer Part Number: ADP1048DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1048 DAUGHTERCARD
• Manufacturer: Analog Devices
• Series: ADP1048r

Specifications of ADP1048DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Dimensions: 40 mm x 25 mm
• Interface Type: I2C
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1048

ADP1047/ADP1048
FREQUENCY SYNCHRONIZATION SET REGISTER
Table 92. Register 0xFE1E—Frequency Synchronization Set
Bits
[7:2]
[1:0]
VOLTAGE LOOP FILTER GAIN REGISTER
Table 93. Register 0xFE20—Voltage Loop Filter Gain
Bits
[7:0]
VOLTAGE LOOP FILTER ZERO REGISTER
Table 94. Register 0xFE21—Voltage Loop Filter Zero
Bits
[7:0]
FAST VOLTAGE LOOP FILTER GAIN REGISTER
Table 95. Register 0xFE22—Fast Voltage Loop Filter Gain
Bits
[7:0]
FAST VOLTAGE LOOP FILTER ZERO REGISTER
Table 96. Register 0xFE23—Fast Voltage Loop Filter Zero
Bits
[7:0]
FAST VOLTAGE LOOP ENABLE REGISTER
Table 97. Register 0xFE24—Fast Voltage Loop Enable
Bits
7
[6:5]
Bit Name
Voltage loop filter
gain
Bit Name
RSVD
Frequency division
Bit Name
Voltage loop filter
zero
Bit Name
Fast voltage loop
filter gain
Bit Name
Fast voltage loop
filter zero
Bit Name
Enable fast loop
for line transient
Regulation band
limit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
Sets the frequency division between the switching frequency and the external SYNC clock
(f
Bit 1
0
0
1
1
Description
Determines the digital filter gain of the PFC fast voltage loop.
Description
Determines the position of the digital filter zero of the PFC fast voltage loop.
Description
Enables fast loop mode immediately after the overshoot becomes larger than the regulation band
plus 3%.
1 = enable fast loop mode.
0 = disable fast loop mode.
Sets the threshold of the regulation band limit for switching from the normal filter to the fast loop
filter.
Bit 6
0
0
1
1
Description
Determines the digital filter gain of the PFC voltage loop.
Description
Determines the position of the digital filter zero of the PFC voltage loop.
SW
/f
SYNC_EXT
Bit 0
0
1
0
1
Bit 5
0
1
0
1
).
Rev. 0 | Page 68 of 84
Frequency Division
1
1/2
1/3
1/4
Threshold
±1.5625%
±3.125%
±6.25%
±12.5%
Data Sheet