MAX98089EVKIT+WLP Maxim Integrated, MAX98089EVKIT+WLP Datasheet - Page 118

• Manufacturer Part Number: MAX98089EVKIT+WLP
• Description: Audio IC Development Tools
• Manufacturer: Maxim Integrated
• Type: Audio CODECr

Specifications of MAX98089EVKIT+WLP

• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX98089
• Operating Supply Voltage: 2.8 V to 5.5 V
• Interface Type: I2C
• Operating Supply Current: 1 A

Device Revision
Table 37. Device Revision Register
The IC features an I
serial interface comprising a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate com-
munication between the IC and the master at clock rates
up to 400kHz. Figure 5 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I, is
required on SDA. SCL operates only as an input. A pullup
resistor, typically greater than 500I, is required on SCL
if there are multiple masters on the bus, or if the single
master has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors pro-
SMBus is a trademark of Intel Corp.
Maxim Integrated
Figure 34. START, STOP, and REPEATED START Conditions
(Read Only)
REGISTER
0xFF
BIT
7
6
5
4
3
2
1
0
2
C/SMBusK-compatible, 2-wire
NAME
REV
SCL
SDA
I
2
C Serial Interface
Device Revision Code
REV is always set to 0x40.
S
Low-Power, Stereo Audio Codec
with FlexSound Technology
Sr
tect the digital inputs of the IC from high voltage spikes
on the bus lines, and minimize crosstalk and undershoot
of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 33). A START condition
from the master signals the beginning of a transmission
to the IC. The master terminates transmission, and frees
the bus, by issuing a STOP condition. The bus remains
active if a REPEATED START condition is generated
instead of a STOP condition.
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the same
SCL high pulse as the START condition.
DESCRIPTION
P
START and STOP Conditions
MAX98089
Early STOP Conditions
Bit Transfer
118