HSC-ADC-EVALDZ Analog Devices, HSC-ADC-EVALDZ Datasheet - Page 8

• Manufacturer Part Number: HSC-ADC-EVALDZ
• Description: Data Conversion IC Development Tools Data Converter Evaluation Platform
• Manufacturer: Analog Devices
• Type: ADCr
• Series: HSC_EVALBOARDr

Specifications of HSC-ADC-EVALDZ

• Rohs: yes
• Product: Evaluation Platforms
• Tool Is For Evaluation Of: ADC Devices
• Interface Type: USB
• Operating Supply Voltage: 12 V
• Operating Supply Current: 3 A
• Factory Pack Quantity: 1
• For Use With: ADC Evaluation Boards

C
B
A
D
AWE_N
8
8
2.5VD
AWE_N_25
FPGA_ASYNC_AMS1
FPGA_D0
FPGA_D1
FPGA_D2
FPGA_D3
FPGA_D4
FPGA_D5
FPGA_D6
FPGA_D7
1
2
OE
A
DGND
2.5VD
C803
0.1UF
5
VCC
GND
3
DGND
Y
U801
NC7SP126P5X
4
22
10
2
3
4
5
6
7
8
9
AWE_N_25
T_R_N
OE_N
A0
A1
A2
A3
A4
A5
A6
A7
DGND
C801
0.1UF
VCCA
1
GND
23
DGND
VCCB
DGND
24
C807
0.1UF
PAD
B0
B1
B2
B3
B4
B5
B6
B7
U803
FXL4245MPX
21
20
19
18
17
16
15
14
1
E/D
7
7
3.3VD
ASYNC_AMS1
3.3VD
DGND
VDD
GND
2
C802
0.1UF
4
DGND
C804
0.1UF
DGND
OUT
CWX823-100.0MHZ
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Y801
3
1
2
OE
A
R801
2.5VD
33
5
VCC
GND
3
DGND
Y
2.5VD
U802
NC7SP126P5X
AWE_N_25
FPGA_ASYNC_AMS1
FPGA_D8
FPGA_D9
FPGA_D10
FPGA_D11
FPGA_D12
FPGA_D13
FPGA_D14
FPGA_D15
4
FPGA
DGND
U806
C805
0.1UF
5
DGND
R806
100K
FPGA_ASYNC_AMS1
1
2
FIN1001M5X
4
3
22
10
2
3
4
5
6
7
8
9
T_R_N
OE_N
A0
A1
A2
A3
A4
A5
A6
A7
DGND
6
6
VCCA
1
GND
23
DGND
VCCB
24
PAD
CLK100+
CLK100-
B0
B1
B2
B3
B4
B5
B6
B7
- BF
U804
FXL4245MPX
21
20
19
18
17
16
15
14
FPGA_ARE_N
FPGA_AWE_N
CLK100+
CLK100-
FPGA_D15
FPGA_D14
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
FPGA_D7
FPGA_D6
FPGA_D5
FPGA_D4
FPGA_RD_RDY
FPGA_FIFO_RST
ADP_SYNC
3.3VD
DGND
C806
0.1UF
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
AG28
AG27
AG26
AA26
AA27
AD28
AD27
AC28
AB28
AF27
AH28
AE28
AE27
AA24
AA25
AC25
AD25
AB27
AB26
AF26
IO_L0P_GC_24
IO_L0N_GC_24
IO_L1P_GC_24
IO_L1N_GC_24
IO_L2P_D15_24
IO_L2N_D14_24
IO_L3P_D13_24
IO_L3N_D12_24
IO_L4P_D11_24
IO_L4N_VREF_D10_24
IO_L5P_D9_24
IO_L5N_D8_24
IO_L6P_D7_24
IO_L6N_D6_24
IO_L7P_D5_24
IO_L7N_D4_24
IO_L8P_SRCC_24
IO_L8N_SRCC_24
IO_L9P_MRCC_24
IO_L9N_MRCC_24
2.5VD
FPGA_ADDR5
FPGA_ADDR4
FPGA_ADDR3
FPGA_ADDR2
FPGA_ADDR1
FPGA_ARE_N
FPGA_AWE_N
INTERFACE,
LED1
LED2
LED3
LED4
DGND
5
5
DO
ALL
C809
0.1UF
NOT
OTHER
LNJ308G8TRA
LNJ308G8TRA
LNJ308G8TRA
LNJ308G8TRA
XC6VLX75T-2FFG784C
C
C
C
C
MOVE
D801
D802
D803
D804
2.5VD
PINS
(GREEN)
(GREEN)
(GREEN)
(GREEN)
A
A
A
A
FSYNC,
VCCO_24
CAN
22
10
2
3
4
5
6
7
8
9
49.9
49.9
49.9
49.9
R802
R803
R804
R805
T_R_N
OE_N
A0
A1
A2
A3
A4
A5
A6
A7
CLK100,
BE
VCCA
1
IO_L14N_VREF_FOE_B_MOSI_24
MOVED
GND
23
DGND
VCCB
FPGA_ARE_N,
24
PAD
TO
2.5VD
IO_L12N_D2_FS2_24
IO_L13P_D1_FS1_24
IO_L13N_D0_FS0_24
IO_L15P_FWE_B_24
IO_L14P_FCS_B_24
IO_L16N_CSO_B_24
IO_L10P_MRCC_24
IO_L10N_MRCC_24
IO_L11P_SRCC_24
IO_L11N_SRCC_24
B0
B1
B2
B3
B4
B5
B6
B7
IO_L15N_RS1_24
IO_L16P_RS0_24
IO_L17P_VRN_24
IO_L17N_VRP_24
HELP
IO_L12P_D3_24
U805
FXL4245MPX
21
20
19
18
17
16
15
14
IO_L18P_24
IO_L18N_24
IO_L19P_24
IO_L19N_24
ROUTING
FPGA_AWE_N
3.3VD
U101
AE25
AF25
AB23
AC23
AC26
AD26
AH26
AH25
AE24
AF24
AG24
AH24
AC24
AB24
AH23
AG23
AE23
AD23
AB22
AA22
DGND
C810
0.1UF
4
4
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ARE_N
AWE_N
OR
FPGA_D#
FPGA_CLKOUT_BUF
FPGA_SPI_MOSI
FPGA_SPI_MISO
FPGA_SPI_CLK
FPGA_D3
FPGA_D2
FPGA_D1
FPGA_D0
LED1
LED2
FPGA_SPI_SEL_A
FPGA_WR_RDY
FPGA_ADDR5
FPGA_ASYNC_AMS1
FPGA_ADDR4
FPGA_ADDR3
LED3
LED4
FPGA_ADDR2
FPGA_ADDR1
PINS
MISC
CLKOUT
USB_CONFIGURED_N
FPGA_SPI_SEL_A
FPGA_SPI_MOSI
FPGA_SPI_MISO
FPGA_SPI_CLK
USB_CONFIGURED_N
FPGA_WR_RDY
FPGA_RD_RDY
FPGA_FIFO_RST
2.5VD
2.5VD
3
3
DGND
DGND
C813
0.1UF
C815
0.1UF
2.5VD
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OE
A
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
2.5VD
2.5VD
VCC
GND
DGND
Y
U807
NC7SV126P5X
15
10
15
10
AN
D
9
3
4
5
6
2
7
9
3
4
5
6
2
7
E
V
OE_N
A0
A1
A2
A3
T_R0_N
T_R1_N
T_R2_N
T_R3_N
OE_N
A0
A1
A2
A3
T_R0_N
T_R1_N
T_R2_N
T_R3_N
A
VCCA
VCCA
C
1
GND
8
1
GND
8
L G
O
E
R807
DGND
DGND
S
33
DGND
0.1UF
PAD
PAD
C811
16
16
VCCB
VCCB
PAD
PAD
FPGA_CLKOUT_BUF
B0
B1
B2
B3
B0
B1
B2
B3
U809
FXL4TD245BQX
U810
FXL4TD245BQX
HADV6
DESIGN VIEW
PTD ENGINEER
-
<PRODUCT_1>
<DESIGN_VIEW>
<PTD_ENGINEER>
14
13
12
11
14
13
12
11
3.3VD
3.3VD
REV
DGND
DGND
C814
0.1UF
C816
0.1UF
2
2
PH13_WR_RDY
PG13_RD_RDY
PH15_FIFO_RST
USB_CONFIGURED
E801
DNI
1
DESCRIPTION
E802
DNI
1
SCHEMATIC
DGND
C812
0.1UF
E803
2
1
DNI
REVISIONS
A
2.5VD
VCC
GND
5
3
E804
1
DGND
DNI
Y
U808
NC7SZ04M5X
4
DRAWING NO.
SIZE
PH9_SPI_SEL_A
PG4_MOSI_SW
PG3_MISO_SW
PG2_SCK_SW
D D D
-
D
R808
100K
USB_CONFIGURED_N
SCALE
<SCALE>
DATE
1
SHEET
1
E805
DNI
1
DGND
8
APPROVED
OF
D
REV
17
D
C
B
A