TWR-P1025 Freescale Semiconductor, TWR-P1025 Datasheet - Page 13

• Manufacturer Part Number: TWR-P1025
• Description: Development Boards & Kits - Other Processors TOWER MODULE P1025
• Manufacturer: Freescale Semiconductor

Specifications of TWR-P1025

• Rohs: yes
• Product: Development Platforms
• Tool Is For Evaluation Of: P1025
• Core: PowerPC e500
• Interface Type: I2C, UART, USB 2.0
• Operating Supply Voltage: 5 V
• For Use With: Freescale Tower System

Hardware Description
3.2
The P1025 takes a single input clock, SYSCLK, as its primary clock source for the e500 cores and all of
the devices and interfaces that operate synchronously with the core. As shown in
input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB)
clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous system
logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB
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Dual high-performance 32-bit cores, built on Power Architecture® technology:
— 32-bit e500v2 PowerPC core
— 36-bit physical addressing
— Double-precision floating-point support
— 32 Kbyte L1 instruction cache and 32 Kbyte L1 data cache for each core
— 400 MHz to 533 MHz clock frequency
256 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory.
Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
— TCP/IP acceleration, quality of service, and classification capabilities
— IEEE® 1588 support
— Lossless flow control
— MII, RMII, RGMII, SGMII
High-speed interfaces supporting various multiplexing options:
— Four SerDes upto 2.5 GHz/lane multiplexed across controllers
— Two PCI Express interfaces
— Two SGMII interfaces
High-speed USB controller (USB 2.0)
— Host and device support
— Enhanced host controller interface (EHCI)
— ULPI interface to PHY
Enhanced secure digital host controller (SD/MMC)
Enhanced serial peripheral interface (eSPI)
Integrated security engine
— Protocol support includes ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS
— XOR acceleration
32-bit DDR3 SDRAM memory controller with ECC support
Programmable interrupt controller (PIC) compliant with OpenPIC standard
One four-channel DMA controller
Two I2C controllers, DUART, timers
Enhanced local bus controller (eLBC)
QUICC Engine block
Clocking
TWR-P1025 Hardware User Guide, Rev. 2
Figure
Freescale Semiconductor
3-1, the SYSCLK