TWR-P1025 Freescale Semiconductor, TWR-P1025 Datasheet - Page 15

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TWR-P1025

Manufacturer Part Number
TWR-P1025
Description
Development Boards & Kits - Other Processors TOWER MODULE P1025
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of TWR-P1025

Rohs
yes
Product
Development Platforms
Tool Is For Evaluation Of
P1025
Core
PowerPC e500
Interface Type
I2C, UART, USB 2.0
Operating Supply Voltage
5 V
For Use With
Freescale Tower System
Hardware Description
4
CPU_SPEED
_SELECT0
SW1.7
ON
LA[29:31] No Default
Functional Signals
TSEC_1588_PULSE_OUT1,
TSEC_1588_PULSE_OUT2
TSEC_1588_CLK_OUT,
LWE0, UART_SOUT1,
Functional Signals
Functional Signals
LGPL2/LOE/LFRE
CPU_SPEED_SELECT1
LBCTL, LALE,
READY_P1
No Default
No Default
No Default
Table 3-2. P1025 e500 Core 0 & 1 to CCB Clock Ratio Selection
SW1.8
ON
Table 3-1. P1025 CCB to SYSCLK Ratio Selection
Reset Configuration Name
Table 3-3. P1025 DDR Clock PLL Ratio
TWR-P1025 Hardware User Guide, Rev. 2
cfg_sys_pll[0:2]
Reset Configuration
Table 3-4. CPU Speed Selection
cfg_core0_pll[0:2]
cfg_core1_pll[0:2]
Reset Configuration
cfg_ddr_pll[0:2]
CORE(0 &1) Speed
Name
Name
(MHz)
533
Value
Value
000
001
010
011
100
101
110
111
000
001
010
Value
QE Speed (MHz)
000
001
010
011
100
101
110
111
266
e500 Core: CCB Clock
CCB Clock : SYSCLK Ratio
e500 Core: CCB Clock
Synchronous mode
3:2 (1.5:1)
5:2 (2.5:1)
Reserved
Reserved
Reserved
Ratio
Reserved
Reserved
1:1
2:1
3:1
Ratio
10:1
3:1
4:1
6:1
8:1
Freescale Semiconductor
4:1
5:1
6:1
SYSCLK (MHz)
66.667

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