DS4830EVKIT# Maxim Integrated, DS4830EVKIT# Datasheet
DS4830EVKIT#
Specifications of DS4830EVKIT#
Related parts for DS4830EVKIT#
DS4830EVKIT# Summary of contents
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... Typical Application Circuit appears at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. For related parts and recommended products to use with this part, refer to: Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels ...
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... PARAMETER Supply Current I Brownout Voltage Brownout Hysteresis 1.8V Regulator Initial Voltage 2.85V Regulator Initial Voltage Maxim Integrated Continuous Source Current ................20mA per pin, 50mA total Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range ............................ -55NC to +125NC + 0.3V)* Lead Temperature (soldering, 10s) ............................ …+300NC DD Soldering Temperature (reflow) .................................. …+260NC ...
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... Pullup Current: MDIO, MDI, MCL, MCS, All GPIO Pins GPIO Drive Strength, Extra Strong Outputs: GP0, GP1, MCS, PW8, PW9 GPIO Drive Strength, Strong Outputs: MDI, DACPW3, DACPW6 GPIO Drive Strength, Excluding Strong GPIO Outputs Maxim Integrated SYMBOL CONDITIONS f OSC +25NC (Note 5) A PERIPHERAL f ...
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... Fast Comparator Operating Current Fast Comparator Full Scale Fast Comparator Integral Nonlinearity Fast Comparator Differential Nonlinearity Fast Comparator Offset Fast Comparator Input Resistance Fast Comparator Input Capacitance Fast Comparator Sample Rate Maxim Integrated Optical Microcontroller SYMBOL CONDITIONS 2.5V internal reference 99% settled I Per channel DACS DACINL 12-bit at 2 ...
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... T = -40NC to +85NC, unless otherwise noted. Typical values are PARAMETER Sample/Hold Input Range Sample/Hold Capacitance Sample Input Leakage Sample Time Hold Time Sample Offset Sample Error Sample Discharge Strength Maxim Integrated SYMBOL CONDITIONS I ADC V FS-ADC1 V FS-ADC2 V FS-ADC3 V FS-ADC4 ADCINL ...
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... Rise Time of Both SDA/MSDA and SCL/MSCL Signals Fall Time of Both SDA/MSDA and SCL/MSCL Signals Setup Time for STOP Condition Spike Pulse Width That Can Be Suppressed by Input Filter SCL/MSCL and SDA/MSDA Input Capacitance SMBusTimeout Maxim Integrated Optical Microcontroller SYMBOL CONDITIONS t Mass erase ME t Page erase PE t ...
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... Inactive SSPICK Input Pulse-Width High/ Low SSPICS Active to First Shift Edge SSPIDI Input to SSPICK Sample Edge Rise/Fall Setup SSPIDI Input from SSPICK Sample Edge Transition Hold SSPIDO Output Valid After SSPICK Shift Edge Transition Maxim Integrated SYMBOL CONDITIONS f SCLOUT t 3WDC ...
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... Note 12: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V bridge the undefined region of the falling edge of SCL. Note 13: C —Total capacitance of one bus line in pF. B Note 14: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. Maxim Integrated Optical Microcontroller SYMBOL CONDITIONS t SSH ...
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... Figure Timing Diagram WRITE MODE MCS t L MCL MDIO READ MODE MCS t L MCL MCS Figure 2. 3-Wire Timing Diagram Maxim Integrated HIGH t t HD:DAT SU:DAT REPEATED R ...
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... MSPIDO MSPIDI Figure 3. SPI Master Communications Timing Diagram SHIFT SSPICS t SSE (SAS = 1) 1/0 SSPICK 0/1 CKPOL/CKPHA 1/1 SSPICK 0/0 CKPOL/CKPHA SSPIDI SSPIDO Figure 4. SPI Slave Communications Timing Diagram Maxim Integrated Optical Microcontroller SAMPLE SHIFT SAMPLE t MSPICK t t MCH MCL t MOH t MOV MSB MSB MIS ...
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... TCK TMS/TDI TDO Figure 5. JTAG Timing Diagram Maxim Integrated Optical Microcontroller V REF DVTH THDX DS4830 Timing Diagrams (continued TLQ 11 ...
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... Digital RST 2 SCL Digital 3 SDA Digital 4 GP0 ADC/Digital Input 5 REG285 V REG 6 GP1 ADC/Digital Input Voltage Supply, ADC Input 8 GP2 SH Input, ADC Input Maxim Integrated TOP VIEW REFINA 31 DACPW0 32 DACPW1 33 34 DACPW2 DACPW3 35 DS4830 36 DACPW4 37 DACPW5 38 DACPW6 ...
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... GP14 ADC/Digital Input 22 GP15 ADC/Digital Input 23 SHEN Digital 24 MDIO Digital 25 MDI Digital 26 MCL Digital Maxim Integrated Optical Microcontroller OUTPUT POWER-ON STRUCTURE STATE (FIRST COLUMN IS DEFAULT FUNCTION) High None ADC-S3 Impedance Push-Pull 55µA Pullup JTAG TCK Push-Pull 55µA Pullup JTAG TDI Push-Pull 55µ ...
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... DACPW2 Digital 35 DACPW3 Digital 36 DACPW4 Digital 37 DACPW5 Digital 38 DACPW6 Digital Reference, ADC/ 39 REFINB Digital Input Maxim Integrated Optical Microcontroller OUTPUT POWER-ON STRUCTURE STATE (FIRST COLUMN IS DEFAULT FUNCTION) Push-Pull, 3-Wire Chip 55µA Pullup Extra Strong Select MCS None V ADC-VDD DD Push-Pull, 55µA Pullup ...
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... SSPICK, SSPICS, SSPIDI, SPI Slave Interface: SSPICK (Clock), SSPICS (Active-Low Chip Select), SSPIDI (Data In), SSPIDO SSPIDO (Data Out). In SPI slave mode, the I TCK, TDI, TDO, TMS JTAG Interface Pins. Also includes RST. Maxim Integrated Optical Microcontroller OUTPUT POWER-ON STRUCTURE STATE Push-Pull 55µ ...
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... GPIO PORT PINS SCL SLAVE: SDA SSPIDO SPI SSPICS DISCH SAMPLE/HOLD SHEN[1:0] ADC-SHP[1:0] ADC-SHN[1:0] Maxim Integrated CLOCK CONTROL, WATCHDOG TIMER, AND POWER MONITOR STACK MEMORY CKCN WDCN IC INTERRUPT ADDRESS LOGIC GENERATION IC IMR LOOP COUNTERS IIR BOOLEAN VARIABLE MANIPULATION ...
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... Module 3: Timer and Counter 2, MAC-Related Registers • Module 4: Digital-to-Analog Converter (DAC) • Module 5: Quick Trips, SPI Master, PWM MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. Maxim Integrated The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca- tions ...
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... More information on the utility ROM contents is contained in the DS4830 User’s Guide. Some applications require protection against unau- thorized viewing of program code memory. For these applications, access to in-system programming, in-appli- cation programming, or in-circuit debugging functions Maxim Integrated PROGRAM MEMORY SPACE FFFFh FFFFh 8FFFh ...
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... ADDRESS IS 36h (1Bh). IS I2C_SPE BIT SET? NO JUMP TO USER CODE (FLASH) AT 0000h. Figure 7. In-System Programming Maxim Integrated Optical Microcontroller Stack Memory system design as well as reduce the life-cycle cost of the embedded system. Programming can be password pro- tected to prevent unauthorized access to code memory. An internal bootstrap loader allows the device to be pro- ...
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... CORE CLOCK Figure 8. System Timing Maxim Integrated The device features several sources that can be used to reset the DS4830. An internal power-on-reset (POR) circuit is used to enhance system reliability. This circuit forces the device Register Set to perform a POR whenever a rising voltage on V ...
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... Each general-purpose timer/counter uses three SFRs. GTCN is the general control register, GTV is the timer value register, and GTC is the timer compare register. Maxim Integrated Optical Microcontroller The timer can be used in two modes: free-running mode and compare mode with interrupts. Both are described in detail in the DS4830 User’ ...
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... There are also two selectable external references. REFINA can be selected as the full-scale reference for DAC0 to DAC3. REFINB can be selected as the full-scale Maxim Integrated Optical Microcontroller reference for DAC4 to DAC7. The DAC outputs are volt- age buffered. Each DAC can be individually disabled and put into a low-power power-down mode using DACCFG ...
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... PGA ADGAIN ADCONV (START CONVERSATION) Figure 9. ADC Block Diagram Maxim Integrated Optical Microcontroller The ADCCLK is derived from the system clock with divi- sion ratio defined by the ADC control register. An A/D conversion takes 15 ADCCLK cycles to complete with additional four core clocks used for data processing. ...
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... Because the quick trips and the ADC use the same input pins, the controller ensures that no colli- sion takes place. SMBus is a trademark of Intel Corp. Maxim Integrated Optical Microcontroller The quick-trip-related SFRs are accessed in module 5. Refer to the quick trip section of the DS4830 User’s Guide for more information ...
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... I/O. However, the SSEL can optionally be used as a mode fault detection in master mode. Maxim Integrated Optical Microcontroller SPI Master Interface The master mode is used when the device’s SPI controls the data transmission rates and data format. The SPI is placed in master mode by setting the master mode bit (MSTM) ...
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... Debug mode can be invoked from background mode. • Debug mode allows the debug engine to take control of the CPU, providing read/write access to internal reg- isters and memory, and single-step trace operation. Maxim Integrated To achieve the best results when using the DS4830, DEBUG decouple the V tor. Use a high-quality, ceramic, surface-mount capaci- tor if possible ...
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... TEMP RANGE DS4830T+ -40NC to +85NC +Denotes a lead(Pb)-free/RoHS-compliant package Tape and reel. *EP = Exposed pad. Maxim Integrated Optical Microcontroller For the latest package outline information and land patterns (foot- PIN-PACKAGE prints www.maximintegrated.com/packages. Note that a 40 TQFN-EP* “+”, “#”, or “-” in the package code indicates RoHS status only. ...
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... MD DFB 25I 25I MD DFB 25I 25I MD DFB 25I 25I MD DFB 25I Maxim Integrated Optical Microcontroller Typical Application Circuit V (+3.3V) CC VCCT VSEL TOUTA R1 MAX3948 SCL TOUTC SDA VOUT CSEL VCCT VSEL TOUTA R2 MAX3948 SCL TOUTC SDA VOUT CSEL VCCT VSEL TOUTA ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...