ATSAMA5D31-EK Atmel, ATSAMA5D31-EK Datasheet - Page 72

• Manufacturer Part Number: ATSAMA5D31-EK
• Description: Development Boards & Kits - ARM EVAL KIT SAMA5D31 CRYPTO
• Manufacturer: Atmel
• Series: SAMA5D3r

Specifications of ATSAMA5D31-EK

• Product: Evaluation Kits
• Tool Is For Evaluation Of: SAMA5D31
• Core: ARM
• Interface Type: Serial, USB
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 bit
• Description/function: Allows users to extensively evaluate, prototype and create application-specific designs
• Dimensions: 165 mm x 135 mm x 20 mm
• Maximum Operating Temperature: + 60 C
• Minimum Operating Temperature: 0 C
• For Use With: SAMA5D31

11180A–ATARM–30-Jan-13
6.4.2
Figure 6-25. JTAG J9
6-24
JTAG/ICE Connector
Table 6-5. JTAG/ICE Connector J9 Signal Descriptions
Pin
10
11
12
1
2
3
4
5
6
7
8
9
Mnemonic
VT
V
nTRST Target Reset -
Active-low output
signal that resets the target.
GND
TDI Test Data Input - Serial
data output line, sampled on
the rising edge of the TCK
signal.
GND
TMS Test Mode Select.
GND
TCK Test Clock - Output
timing signal, for
synchronizing test logic and
control register access.
GND
RTCK - Input Return Test
Clock signal from the target.
GND
supply
ref
3.3V power
3.3V power
Signal Description
This is the target reference voltage. It is used to check if the
target has power, to create the logic-level reference for the
input comparators, and to control the output logic levels to the
target. It is normally fed from VDD on the target board and
must not have a series resistor.
This pin is not connected in SAM-ICE. It is reserved for
compatibility with other equipment. Connect to VDD or leave
open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the
target JTAG port. Typically connected to nTRST on the target
CPU. This pin is normally pulled High on the target to avoid
unintentional resets when there is no connection.
Common ground
JTAG data input of target CPU. It is recommended that this pin
is pulled to a defined state on the target board. Typically
connected to TDI on target CPU.
Common ground
JTAG mode set input of target CPU. This pin should be pulled
up on the target. Typically connected to TMS on target CPU.
Output signal that sequences the target's JTAG state
machine, sampled on the rising edge of the TCK signal.
Common ground
JTAG clock signal to target CPU. It is recommended that this
pin is pulled to a defined state on the target board. Typically
connected to TCK on target CPU.
Common ground
Some targets must synchronize the JTAG inputs to internal
clocks. To assist in meeting this requirement, a returned and
retimed TCK can be used to dynamically control the TCK rate.
SAM-ICE supports adaptive clocking which waits for TCK
changes to be echoed correctly before making further
changes. Connect to RTCK if available, otherwise to GND.
Common ground
SAMA5D3x-EK User Guide