78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 56
78M6610+PSU/EK#1
Manufacturer Part Number
78M6610+PSU/EK#1
Description
Development Boards & Kits - Other Processors 78M6610 EVAL KIT
Manufacturer
Maxim Integrated
Datasheet
1.78M6610PSUEK1.pdf
(63 pages)
Specifications of 78M6610+PSU/EK#1
Rohs
yes
Part # Aliases
90-X6610#KK1
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5.5.2 SPI Slave Port
78M6610+PSU Data Sheet
5.5 Timing Specifications
5.5.1 RESET
1
1
56
Parameter
Reset pulse fall time
Reset pulse width
Parameter
t
t
SPCK
t
t
t
t
t
t
t
Guaranteed by design, not subject to test.
Guaranteed by design, not subject to test.
SPILead
SPILag
SPIcyc
SPIW
SPISCK
SPIDIS
SPIEV
SPISU
SPIH
SDO
SSB
SDI
SPCK cycle time
Enable lead time
Enable lag time
SPCK pulse width:
SSB to first SPCK fall
Disable time
SPCK to Data Out (SDO)
Data input setup time (SDI)
Data input hold time (SDI)
High
Low
t
SPISCK
t
SPILead
t
SPISU
MSB IN
MSB OUT
t
SPIH
t
Figure 22: SPI Slave Port Timing
SPIW
t
SPIcyc
Ignore if SPCK is low
when SSB falls.
Condition
Condition
t
SPIEV
Min
Min
250
250
15
10
t
–
–
1
0
–
–
5
SPIW
LSB IN
LSB OUT
Typ
Typ
1
5
2
0
–
–
–
–
–
–
–
1
1
1
1
t
SPILag
Max
Max
25
–
–
–
–
–
–
–
–
–
–
t
SPIDIS
Unit
Unit
µs
µs
Rev 1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
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