ADP5586CB-EVALZ Analog Devices, ADP5586CB-EVALZ Datasheet - Page 14

• Manufacturer Part Number: ADP5586CB-EVALZ
• Description: Interface Development Tools
• Manufacturer: Analog Devices
• Type: I/O Expansionr
• Series: ADP5586r

Specifications of ADP5586CB-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP5586
• Interface Type: I2C
• Operating Supply Voltage: 1.65 V to 3.6 V
• Description/function: Evaluation board for keypad decoder and I/O expander
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 30 uA
• For Use With: ADP5586

ADP5586
LOGIC BLOCK
Several of the
and outputs for implementing some common logic functions.
The R1, R2, and R3 input/output pins can be used as inputs,
and the R0 input/output pin can be used as an output for the
logic block. When the R1, R2, and R3 input lines are used, the
GPIO_4_INP_EN, GPIO_3_INP_EN, and GPIO_2_INP_EN
bits (Register 0x29, Bits[3:1]) must be enabled to accept inputs.
ADP5586
LC
LB
LA
input/output lines can be used as inputs
R3_EXTEND_CFG = 1
LC
LC
LB
LB
LA
LA
LC_INV
LB_INV
0
1
0
1
LA_INV
0
1
SEL
SEL
SEL
OUT
OUT
OUT
R3_EXTEND_CFG
IN_LC
IN_LB
LOGIC_SEL[2:0]
IN_LA
(R1)
(R2)
(R3)
RESET_TRIG_TIME[3:0]
FF_CLR
FF_SET
RESET_EVENT_A[7:0]
RESET_EVENT_B[7:0]
RESET_EVENT_C[7:0]
LA_INV
LB_INV
LC_INV
LY_INV
LOGIC_INT_LEVEL
LOGIC_EVENT_EN
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
LA
LB
LC
FF_CLR
LOGIC BLOCK
D
CLR
Figure 19. Logic Block Internal Makeup
SET
XOR
AND
OR
FF_SET
Q
Figure 18. Logic Block Overview
0
1
SEL
Rev. 0 | Page 14 of 44
GENERATOR
OUT
EVENT/INT
XOR
AND
OR
LOGIC
0
1
0
1
0
1
D
LY (R0)
SEL
SEL
SEL
SET
CLR
LOGIC EVENT
KEY EVENT
OUT
OUT
OUT
GPI EVENT
I
2
Q
C BUSY
EVENT_INT
LOGIC_INT
When the R0 pin is used as an output for the logic block, the
GPIO_1_OUT_EN bit (Register 0x27, Bit 0) must be enabled.
The outputs from the logic block can be configured to generate
interrupts. They can also be configured to generate events on
the FIFO.
Figure 19 shows a detailed diagram of the internal makeup of
the logic block, illustrating the possible logic functions that can
be implemented.
AND
OR
XOR
FF
UPDATE
FIFO
IN_LA
IN_LB
IN_LC
GND
AND
XOR
OR
FF
LOGIC_SEL[2:0]
OVRFLOW_INT
000
001
010
011
100
101
110
111
SEL[2:0]
EC[4:0]
MUX
FIFO
OUT
LY
LY
0
1
LY_INV
SEL
OUT
LY
Data Sheet