IS42S16400F-7TL-TR ISSI, Integrated Silicon Solution Inc, IS42S16400F-7TL-TR Datasheet - Page 6

• Manufacturer Part Number: IS42S16400F-7TL-TR
• Description: IC SDRAM 64MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400F-7TL-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16400F
IC42S16400F
6
TRUTH TABLE – COMMANDS AND DQM OPERATION
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
FUNCTION
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank/column, start READ burst)
WRITE (Select bank/column, start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
auto precharge; BA0, BA1 determine which bank is being read from or written to.
(2)
(8)
(8)
(6,7)
(3)
(4)
(4)
(5)
CS
—
—
H
L
L
L
L
L
L
L
L
RAS
—
—
H
H
H
H
X
L
L
L
L
CAS
—
—
X
H
H
H
H
L
L
L
L
Integrated Silicon Solution, Inc. — www.issi.com
(1)
WE
—
—
H
H
H
H
X
L
L
L
L
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
(8)
(8)
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
—
—
X
X
X
X
High-Z
Active
Active
Valid
DQs
03/19/08
X
X
X
X
X
X
X
Rev. A