KITMMA9550LEVM Freescale Semiconductor, KITMMA9550LEVM Datasheet - Page 21

• Manufacturer Part Number: KITMMA9550LEVM
• Description: Acceleration Sensor Development Tools EVM KIT FOR MMA9550L
• Manufacturer: Freescale Semiconductor

Specifications of KITMMA9550LEVM

• Rohs: yes
• Tool Is For Evaluation Of: MMA955xL
• Acceleration: 2 g, 4 g, 8 g
• Sensing Axis: Triple Axis
• Interface Type: I2C, SPI
• Operating Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Current: 3.1 mA
• Output Type: Analog, Digital

Table 14. Master I
1.
2.
3.
4.
4.14
This device includes a slave I
includes a master/slave I
4.14.1
Table 13. I
1.
2.
4.14.2
The master I
module across frames in which a portion of the time is spent in low-speed mode.
Sensors
Freescale Semiconductor, Inc.
SCL clock frequency
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time for I
Data setup time
Setup time for STOP condition
Bus-free time between STOP and START condition
Pulse width of spikes that must be suppressed by the input filter
Standard
Fast
Fast +
High-speed
SDA
SCL
supported
The maximum t
Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual
(MMA955xLRM).
The master mode I
ative hold time can result, depending on the edge rates of the SDA and SCL lines.
The maximum t
Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.
A fast-mode I
ically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr
line is released.
Mode
t
f
S
2
I
Slave I
Master I
C Speed Ranges
2
2
C module should only be used when the system clock is running at full rate. Do not attempt to use the master I
C Timing
2
C bus device can be used in a Standard mode I
t
HD; DAT
HD; STA
HD; DAT
Rate (f
t
Max Baud
2
LOW
400 KHz
100 KHz
2.0 MHz
2
C-bus devices
2
1 MHz
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a neg-
C timing
2
must be met only if the device does not stretch the LOW period (t
C
must be at least a transmission time less than t
2
Characteristic
SCL
C Timing
2
C module that should be used only during CPU run mode (Φ
)
t
r
2
Minimum
Bit Time
C module that can be used to control the sensor and can be active 100 percent of the time. It also
2.5 μs
0.5 μs
10 μs
t
HD; DAT
1 μs
max +
Figure 12. I
t
SU; DAT
Minimum SCL Low
t
SU; DAT
t
HIGH
500 ns
200 ns
(t
4.7 μs
1.3 μs
= 1000 + 250 = 1250 ns (according to the Standard-mode I
LOW
)
2
2
t
f
C standard and fast-mode timing
C bus system, but the requirement t
t
SU; STA
VD;DAT
Minimum SCL High
Symbol
t
t
t
t
t
HD; STA
HD; DAT
SU; DAT
SU; STO
SU; STA
t
t
f
t
HIGH
LOW
BUF
t
SCL
SP
or t
(t
260 ns
200 ns
0.6 μs
VD;ACK
4 μs
HIGH
SR
)
. For details, see the I
LOW
250
Min
N/A
0
4.0
4.7
4.0
4.7
4.0
4.7
Standard Mode
0
(1)
) of the SCL signal.
(3)
t
HD; STA
Min Data setup Time
SU; DAT
3.45
(t
≥ 250 ns must then be met. This will automat-
D
Max
10 ns
100
N/A
SU; DAT
250 ns
100 ns
—
—
—
—
—
—
—
50 ns
).
2
(2)
C standard.
(2)
t
SP
2
t
SU; STO
)
C bus specification) before the SCL
100
Min
0
0.6
1.3
0.6
0.6
0.6
1.3
0
(3)
0
(1)
Fast Mode
Min/Max Data Hold Time
(4)
0 ns/70 ns (100 pf)
t
r
0 μs/3.45 μs
0 μs/0.45 μs
0 μs/0.9 μs
P
(t
0.9
HD; DAT
Max
400
—
—
—
—
—
—
—
50
(2)
t
BUF
MMA955xL
)
(1)
(1)
(1)
S
Unit
(2)
kHz
μs
μs
μs
μs
μs
ns
µs
µs
ns
2
21
C