ZSPM4551KIT V1.0 ZMDI, ZSPM4551KIT V1.0 Datasheet - Page 16

• Manufacturer Part Number: ZSPM4551KIT V1.0
• Description: Power Management IC Development Tools Li/Ion converter Kit
• Manufacturer: ZMDI
• Type: Battery Managementr

Specifications of ZSPM4551KIT V1.0

• Product Category: Power Management IC Development Tools
• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: ZSPM4551
• Input Voltage: 3.5 V to 7.2 V
• Output Voltage: 3.94 V to 4.18 V
• Interface Type: I2C
• Output Current: 1.5 A

2.3.
The ZSPM4551 features an I
standard and fast mode data rates and auto-sequencing, and it is compliant to I
I
configurability allows optimum charging conditions in a wide range of Li-Ion batteries. I
fault and warning indicators. Whenever a fault is detected, the associated status bit in the STATUS register is set
and the NFLT pin is pulled low. Whenever a warning is detected, the associated status bit in the STATUS register
is set, but the NFLT pin is not pulled low. Reading the STATUS register resets the fault and warning status bits,
and the NFLT pin is released after all fault status bits have been reset.
2.3.1.
Figure 2.3
2.3.2.
The ZSPM4551’s I
(see Figure 2.4). SDA must be connected to a positive supply (e.g., the VDD pin) through an external pull-up
resistor. The devices communicating on this bus can drive the SDA line low or release it to high impedance. To
ensure proper operation, setup and hold times must be met (see Table 1.5). The device that initiates the I
transaction becomes the master of the bus.
Communication is initiated by the master sending a START condition, which is a high-to-low transition on SDA
while the SCL line is high. After the START condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (read = 1; write = 0). After receiving the valid address byte, the device
responds with an acknowledge (ACK). An ACK is a low on SDA during the high of the ACK-related clock pulse.
On the I
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as START
or STOP control conditions. A low-to-high transition on SDA while the SCL input is high indicates a STOP
condition and is sent by the master.
2
Data Sheet
December 4, 2012
C™ operation offers configuration control for termination voltages, charge currents, and charge timeouts. This
ZSPM4551
High-Efficiency Charger for Li-Ion Batteries
Serial Interface
2
C™ bus, during each clock pulse, only one data bit is transferred. The data on the SDA line must remain
I
I
2
2
C™ Subaddress Definition
C™ Bus Operation
Subaddress in I
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
2
C™ is a two-wire serial interface; the two lines are serial clock (SCL) and serial data (SDA)
2
C™ Transmission
2
C™ slave interface that offers advanced control and diagnostic features. It supports
2
C™ standard version 3.0.
2
C™ operation also offers
16 of 30
2
C™