NCV8871LVBGEVB ON Semiconductor, NCV8871LVBGEVB Datasheet - Page 9

• Manufacturer Part Number: NCV8871LVBGEVB
• Description: Power Management IC Development Tools NCV8871 EVAL BOARD
• Manufacturer: ON Semiconductor

Specifications of NCV8871LVBGEVB

• Rohs: yes

Current Mode Control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse−by−pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This allows for a simpler compensation.
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Current Limit
peak current mode and over current latch off. When the
current sense amplifier detects a voltage above the peak
current limit between ISNS and GND after the current limit
leading edge blanking time, the peak current limit causes the
power switch to turn off for the remainder of the cycle. Set
the current limit with a resistor from ISNS to GND, with R
= V
The NCV8871 incorporates a current mode control
The NCV8871 also includes a slope compensation
The NCV8871 features two current limit protections,
CL
/ I
limit
.
NCV8871
PWM Comparator
Oscillator
−
+
+
Voltage Error
Compensation
Figure 11. Current Mode Control Schematic
Slope
CSA
S
R
Q
Compensation
THEORY OF OPERATION
VEA
−
+
http://onsemi.com
+
−
Gate
Drive
9
over current threshold voltage the device enters over current
hiccup mode. The device will remain off for the hiccup time
and then go through the soft−start procedure.
Short Circuit Protection
will attempt to protect the power MOSFET from damage.
When the output voltage falls below the short circuit trip
voltage, after the initial short circuit blanking time, the
device enters short circuit latch off. The device will remain
off for the hiccup time and then go through the soft−start.
EN/SYNC
a dc logic high (CMOS/TTL compatible) voltage is applied
to this pin the NCV8871 operates at the programmed
frequency. When a dc logic low voltage is applied to this pin
the NCV8871 enters a low quiescent current sleep mode.
When a square wave of at least %f
switching frequency is applied to this pin, the switcher
operates at the same frequency as the square wave. If the
signal is slower than this, it will be interpreted as enabling
and disabling the part. The falling edge of the square wave
corresponds to the start of the switching cycle. If device is
disabled, it must be disabled for 7 clock cycles before being
re−enabled.
UVLO
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
GDRV
V
I
SNS
FB
If the voltage across the current sense resistor exceeds the
If the short circuit enable bit is set (SCE = Y) the device
The Enable/Synchronization pin has three modes. When
Input Undervoltage Lockout (UVLO) is provided to
L
V
IN
V
C
OUT
O
R
sync,min
L
of the free running