ADP2442-EVALZ Analog Devices, ADP2442-EVALZ Datasheet - Page 16

• Manufacturer Part Number: ADP2442-EVALZ
• Description: Power Management IC Development Tools Eval board
• Manufacturer: Analog Devices
• Type: DC/DC Converters, Regulators & Controllersr
• Series: ADP2442r

Specifications of ADP2442-EVALZ

• Rohs: yes
• Tool Is For Evaluation Of: ADP2442
• Factory Pack Quantity: 1

THEORY OF OPERATION
The
down, synchronous switching regulator that is capable of driving
1 A loads. The device operates with a wide input voltage range
from 4.5 V to 36 V, and its output is adjustable from 0.6 V to
0.9 V × V
and the low-side N-channel power MOSFET yield high efficiency
at medium to heavy loads. Pulse skip mode is available to improve
efficiency at light loads.
The
voltage, switching frequency, and power good. These features
are programmed externally via tiny resistors and capacitors. The
ADP2442
hysteresis, output short-circuit protection, and thermal shutdown.
CONTROL ARCHITECURE
The
control architecture. The
frequency and pulse skip modes.
Fixed Frequency Mode
A basic block diagram of the control architecture is shown in
Figure 52. The
mode. The output voltage, V
FB. An error amplifier integrates the error between the feedback
voltage (V
an error voltage at the COMP pin.
A current sense amplifier senses the valley inductor current (I
during the off period when the low-side power MOSFET is on
and the high-side power MOSFET is off. An internal oscillator
initiates a pulse-width modulation (PWM) pulse to turn off the
low-side power MOSFET and turn on the high-side power
MOSFET at a fixed switching frequency.
When the high-side N-channel power MOSFET is enabled, the
valley inductor current information is added to an emulated
ramp signal and the PWM comparator compares this value to
the error voltage on the COMP pin. The output of the PWM
comparator modulates the duty cycle by adjusting the trailing
edge of the PWM pulse that turns off the high-side power
MOSFET and turns on the low-side power MOSFET.
Slope compensation is programmed internally into the emulated
ramp signal and is automatically selected, depending on the
input voltage, output voltage, and switching frequency. This
prevents subharmonic oscillations for near or greater than 50%
duty cycle operation. The one restriction of this feature is that
the inductor ripple current must be set between 0.2 A and 0.5 A
to provide sufficient current information to the loop.
ADP2442
ADP2442
ADP2442
ADP2442
IN
also includes protection features, such as UVLO with
FB
. The integrated high-side N-channel power MOSFET
) and the reference voltage (V
is a fixed frequency, current mode control, step-
includes programmable features, such as output
is based on an emulated peak current mode
ADP2442
ADP2442
can be configured in fixed frequency
OUT
, is sensed on the feedback pin,
can operate in both fixed
REF
= 0.6 V) to generate
Rev. 0 | Page 16 of 36
L
)
Pulse Skip Mode
The
SYNC/MODE pin to AGND. In this mode, the pulse skip cir-
cuitry turns on during light loads, switching only as necessary
to keep the output voltage within regulation. This mode allows the
regulator to maintain high efficiency during operation with light
loads by reducing switching losses. The pulse skip circuitry
includes a comparator, which compares the COMP voltage to a
fixed pulse skip threshold.
With light loads, the output voltage discharges at a very slow
rate (load dependent). When the output voltage is within regula-
tion, the device enters sleep mode and draws a very small quiescent
current. As the output voltage drops below the regulation voltage,
the COMP voltage rises above the pulse skip threshold. The
device wakes up and begins switching until the output voltage
is within regulation.
As the load increases, the settling value of the COMP voltage
increases. At a particular load, COMP settles above the pulse skip
threshold, and the device enters the fixed frequency mode. There-
fore, the load current at which COMP exceeds the pulse skip
threshold is defined as the pulse skip current threshold; the
value varies with the duty cycle and the inductor ripple current.
The measured value of pulse skip threshold over V
Figure 19, Figure 20, and Figure 21.
g
COMP
M
ADP2442
REF
V
FB
COMPARATOR
V
RAMP
Figure 52. Control Architecture Block Diagram
THRESHOLD
PULSE SKIP
pulse skip mode is enabled by connecting the
DC
CLOCK
COMP
EMULATION
Figure 53. Pulse Skip Comparator
VC
BLOCK
RAMP
1V
S
R
Q
Q
PWM
SENSE_
OUT
DRIVER
G
CS
ADP2442
CONTROL
LOGIC
R
SWL
× I
Data Sheet
L
V
IN
IN
I
L
is shown in
V
OUT