EVAL-ADM1276EBZ Analog Devices, EVAL-ADM1276EBZ Datasheet - Page 20

• Manufacturer Part Number: EVAL-ADM1276EBZ
• Description: Power Management IC Development Tools EVALUATION BOARD
• Manufacturer: Analog Devices
• Type: Hot Swap & Power Distributionr
• Series: ADM1276r

Specifications of EVAL-ADM1276EBZ

• Rohs: yes
• Tool Is For Evaluation Of: ADM1276
• Input Voltage: 20 V
• Factory Pack Quantity: 1

ADM1276
The VCAP pin has a 2.7 V internal generated voltage that can
be used to set a voltage at the ISET pin. Assuming that V
equals the voltage on the ISET pin, size the resistor divider to
set the ISET voltage as follows:
where V
The VCAP rail can also be used as the pull-up supply for setting
the I
To guarantee accuracy specifications, do not load the VCAP pin
by more than 100 µA.
SOFT START
A capacitor connected to the SS pin determines the inrush
current profile. Before the FET is enabled, the output voltage of
the current-limit reference selector block is clamped at 100 mV.
This, in turn, holds the hot swap sense voltage current limit,
V
request to turn on, the SS pin is held at ground until the voltage
between the SENSE+ and SENSE− pins (V
circuit breaker voltage, V
where V
When the load current generates a sense voltage equal to V
a 10 µA current source is enabled, which charges the SS capa-
citor and results in a linear ramping voltage on the SS pin. The
current-limit reference also ramps up accordingly, allowing the
regulated load current to ramp up while avoiding sudden
transients during power-up. The SS capacitor value is given by
where:
I
t = SS ramp time.
For example, a 10 nF capacitor gives a soft start time of 1 ms.
Note that the SS voltage may intersect with the FLB (foldback)
voltage, and the current-limit reference may change to follow
SS
SENSECL
= 10 µA.
2
V
V
C
C address. Do not use the VCAP pin for any other purpose.
ISET
CB
SS
, at approximately 2 mV. When the FET receives a
SENSE
CBOS
Figure 47. Adjustable 5 mV to 25 mV Current Sense Limit
= V
=
= V
I
V
SENSECL
is typically 0.88 mV, making V
SS
is the current sense voltage limit.
SENSE
ISET
×
C1
t
× 50
− V
CBOS
R2
R1
VCAP
CB
ISET
.
ADM1276
GND
SENSE
CB
= 1.12 mV.
) reaches the
ISET
CB
Rev. B | Page 20 of 48
,
FLB (see Figure 45). This change has minimal impact on startup
because the output voltage rises at a similar rate to the SS voltage.
FOLDBACK
Foldback is a method to actively reduce the current limit as the
voltage drop across the FET increases. It keeps the power across
the FET to a minimum during power-up, overcurrent, or short-
circuit events. It also avoids the need to oversize the FET to
accommodate worst-case conditions, resulting in board size and
cost savings.
The ADM1276 detects the voltage drop across the FET by
looking at a resistor divided version of the output voltage. It is
assumed that the supply voltage remains constant and within
tolerance. The device, therefore, relies on the principle that the
drain of the FET is at the maximum expected supply voltage,
and that the magnitude of the output voltage is relative to that
of the V
voltage to the FLB pin, a relationship from V
to V
Design the resistor divider to output a voltage equal to ISET
when V
below the working tolerance of the supply rail. As V
to drop, the current-limit reference follows V
now the lowest voltage input to the current-limit reference
selector block. This results in a reduction of the current limit
and, therefore, the regulated load current. To prevent complete
current flow restriction, a clamp becomes active when the
current-limit reference reaches 200 mV. The current limit
cannot drop below this level.
To suit the SOA characteristics of a particular FET, the required
minimum current for this clamp varies from design to design.
However, the current-limit reference fixes this clamp at 200 mV,
which equates to 4 mV at the sense resistor. Therefore, the main
ISET voltage can be adjusted to align this clamp to the required
percentage current reduction. For example, if ISET equals 0.8 V,
the clamp can be set at 25% of the maximum current.
FLB
can be derived.
OUT
DS
ISET
of the FET. Using a resistor divider from the output
SS
falls below the desired level. This should be well
VCAP
10µA
SELECT
CURRENT
LIMIT
1.0V
REF
SENSE+
Figure 48. Soft Start
+
×50
CURRENT
CONTROL
SENSE–
–
LIMIT
+
–
GND
CURRENT
LIMIT
DRIVE/
LOGIC
GATE
ADM1276
TIMEOUT
V
CP
OUT
FLB
Data Sheet
, and thus V
GATE
FLB
because it is
OUT
continues
DS
,