ZL8101-30AEV2Z Intersil, ZL8101-30AEV2Z Datasheet
ZL8101-30AEV2Z
Specifications of ZL8101-30AEV2Z
Related parts for ZL8101-30AEV2Z
ZL8101-30AEV2Z Summary of contents
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... VTRK VMON VR V25 R3 C12 C11 FIGURE 1. ZL8101_30AEV2Z 30A DEMO BOARD SIMPLIFIED SCHEMATIC 1 September 6, 2012 AN1781.0 Intersil (and design), Zilker Labs (and design), and PowerNavigator are trademarks owned by Intersil Corporation or one of its subsidiaries. Key Features • 30A Synchronous Buck Converter • Optimized for High Current and High Efficiency • ...
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... Power and load connections are provided through plug-in sockets. A majority of the features of the ZL8101 such as soft-start delay and ramp times, supply sequencing, voltage tracking, and voltage margining are available on this board. For voltage ...
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... ISENA SENB ISENB 15 FB FB- 4 SA1 V0 SA0 DGND C11 10uF 10V XX5 FIGURE 2. ZL8101_30AEV2Z 30A DEMO BOARD COMPLETE CIRCUIT C15 22uF 16V C5 L1 1uF 0.220nH 16V VOUT C24 C6 100uF 100uF 680uF 680uF 1.18K 1uF 6.3V 6. ...
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... R13 100K JP1 R15 10.0K MSTR_EN HW_EN R17 49.9 C21 C23 0.1uF 1uF 10V 25V FIGURE 3. ZL8101_30AEV2Z 30A DEMO BOARD – INTERFACE CIRCUITRY REG1117A VIN VOUT VOUT G-ADJ 1 C25 10uF R28 C12 ...
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... The top view of the ZL8101_30AEV2Z 30A Demo Board is shown in Figure 4, and the most important parts of the board are covered in Table 1 5 Application Note 1781 1 6 20 2 1 15 4 5 FIGURE 4. ZL8101_30AEV2Z 30A DEMO BOARD GUIDE ...
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Board Layout – 6 Layers 8 Application Note 1781 FIGURE 5. PCB - TOP LAYER AN1781.0 September 6, 2012 ...
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Board Layout – 6 Layers (Continued) 9 Application Note 1781 FIGURE 6. PCB - INNER LAYER 1 (VIEWED FROM TOP) AN1781.0 September 6, 2012 ...
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Board Layout – 6 Layers (Continued) 10 Application Note 1781 FIGURE 7. PCB - INNER LAYER 2 (VIEWED FROM TOP) AN1781.0 September 6, 2012 ...
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Board Layout – 6 Layers (Continued) 11 Application Note 1781 FIGURE 8. PCB - INNER LAYER 3 (VIEWED FROM TOP) AN1781.0 September 6, 2012 ...
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Board Layout – 6 Layers (Continued) 12 Application Note 1781 FIGURE 9. PCB - INNER LAYER 4 (VIEWED FROM TOP) AN1781.0 September 6, 2012 ...
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Board Layout – 6 Layers (Continued) 13 Application Note 1781 FIGURE 10. PCB - BOTTOM LAYER (VIEWED FROM TOP) AN1781.0 September 6, 2012 ...
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... Default Configuration Text The following text is loaded into the ZL8101 device on the board as default settings. Each PMBus command is loaded via the PowerNavigator software. The # symbol is used for a comment line. # Zilker Labs 8101 6/7/2012 # ZL Configuration File Revision A # Schematic revision level # BOM revision level ...
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UT_FAULT_RESPONSE DEADTIME DEADTIME_CONFIG DEADTIME_MAX MAX_DUTY TRACK_CONFIG INTERLEAVE #SEQUENCE MFR_CONFIG NLR_CONFIG TEMPCO_CONFIG MISC_CONFIG ISHARE_CONFIG AUTO_COMP_CONFIG PID_TAPS USER_CONFIG DDC_GROUP #DDC_CONFIG INDUCTOR ON_OFF_CONFIG STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL 15 Application Note 1781 0x00 0x0C0C 0x8686 0x0C0C 94 0x00 0x0000 0x0000 0x6A10 0x00000000 0x28 0x2000 0x0000 0x79 ...
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... Measured Data The following data was acquired using a ZL8101_30AEV2Z 30A Demo Board. EFFICIENCY FIGURE 11. EFFICIENCY FOR DIFFERENT OUTPUT VOLTAGES, V TURNON RAMP V = 12V OUT T = 5ms, MIN DUTY = DISABLED RISE AUTOCOMP = OFF MINIMUM DUTY CYCLE ARTIFACT 16 Application Note 1781 ...
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Application Note 1781 TURN OFF RAMP V = 12V 1V 533kHz 15A IN OUT SW OUT T = 5ms, MIN DUTY = DISABLED FALL AUTOCOMP = OFF 5ms FIGURE 13. RAMP DOWN TRANSIENT RESPONSE ...
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... IN OUT FIGURE 15. OUTPUT VOLTAGE RIPPLE WHEN 25A, V References [1] ZL8101 Data Sheet, Zilker Labs, Inc., 2012. [2] AN2033 – PMBus™ Command Set, Zilker Labs, Inc., 2009. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding ...