MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 14
![IC SDRAM 128MBIT 167MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC4M32B2P-6:G
Manufacturer Part Number
MT48LC4M32B2P-6:G
Description
IC SDRAM 128MBIT 167MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2P-6:G
Package / Case
86-TSOPII
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
RoHS Compliant
Memory Case Style
TSOP
No. Of Pins
86
Operating Temperature Range
0°C To +70°C
Operating Temperature Max
70°C
Operating Temperature Min
0°C
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Configuration
4 BLK (1M X 32)
Interface Type
LVTTL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON
Quantity:
7 100
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON
Quantity:
4 000
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
TI
Quantity:
50
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON32
Quantity:
1 036
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON/美光
Quantity:
20 000
Table 6:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Burst Definition
Notes:
1. For a BL = 2, A1–A7 select the block-of-two burst; A0 selects the starting column within the
2. For a BL = 4, A2–A7 select the block-of-four burst; A0–A1 select the starting column within
3. For a BL = 8, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within
4. For a full-page burst, the full row is selected and A0–A7 select the starting column.
5. Whenever a boundary of the block is reached within a given sequence above, the following
6. For a BL = 1, A0–A7 select the unique column to be accessed, and mode register bit M3 is
Full Page
block.
the block.
the block.
access wraps within the block.
ignored.
Length
Burst
(256)
2
4
8
n = A0–A7 (Location
Starting Column
A2
0
0
0
0
1
1
1
1
Address
0–256)
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
14
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Type = Sequential
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn - 1, Cn…
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0