MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 39
![IC SDRAM 128MBIT 167MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC4M32B2P-6:G
Manufacturer Part Number
MT48LC4M32B2P-6:G
Description
IC SDRAM 128MBIT 167MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2P-6:G
Package / Case
86-TSOPII
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
RoHS Compliant
Memory Case Style
TSOP
No. Of Pins
86
Operating Temperature Range
0°C To +70°C
Operating Temperature Max
70°C
Operating Temperature Min
0°C
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Configuration
4 BLK (1M X 32)
Interface Type
LVTTL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON
Quantity:
7 100
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON
Quantity:
4 000
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
TI
Quantity:
50
Company:
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON32
Quantity:
1 036
Part Number:
MT48LC4M32B2P-6:G
Manufacturer:
MICRON/美光
Quantity:
20 000
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
state for precharging.
less of bank.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Accessing mode
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
Refreshing: Starts with registration of an AUTO REFRESH command and ends
register:
when
banks idle state.
Starts with registration of a LOAD MODE REGISTER command and
ends when
be in the all banks idle state.
when
39
t
t
RFC is met. Once
RP is met. Once
t
MRD has been met. Once
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, all banks will be in the idle state.
t
RFC is met, the SDRAM will be in the all
t
MRD is met, the SDRAM will
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition