IS43R32800B-5BL ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL Datasheet - Page 20

• Manufacturer Part Number: IS43R32800B-5BL
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32800B-5BL

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 400mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R32800B
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Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as
shown in Figure “CAS LATENCY”. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When
a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1--Ai when the burst length is set to two, by A2--Ai when the burst
length is set to four and by A3--Ai when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both read and write bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this
is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column address, as shown in Table “BURST DEFINITION”.
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of
the first piece of output data. If a READ command is registered at clock edge n, and the latency is m clocks, the
data will be available nominally coincident with clock edge n + m.
Reserved states should not be used as unknown operation, or incompatibility with future versions may result.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08