MT48V8M16LFB4-8 IT:G Micron Technology Inc, MT48V8M16LFB4-8 IT:G Datasheet - Page 24
![IC SDRAM 128MBIT 125MHZ 54VFBGA](/photos/7/22/72286/557-54-fbga_sml.jpg)
MT48V8M16LFB4-8 IT:G
Manufacturer Part Number
MT48V8M16LFB4-8 IT:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Specifications of MT48V8M16LFB4-8 IT:G
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
BURST TERMINATE
AUTO REFRESH
SELF REFRESH
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode where auto precharge does not apply. Auto precharge is nonpersis-
tent in that it is either enabled or disabled for each individual read or write command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in “Operation” on
page 25.
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the Operation section of this data
sheet. The BURST TERMINATE command does not precharge the row; the row will
remain open until a PRECHARGE command is issued.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
PRECHARGE command as shown in the operation section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires
4,096 AUTO REFRESH cycles every 64ms (
distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement
and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands
can be issued in a burst at the minimum cycle rate (
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of 2 clocks, regardless of clock frequency) for
t
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less because both SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
XSR because time is required for the completion of any internal refresh in progress.
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
24
t
RAS and may remain in self refresh mode for an
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF), regardless of width option. Providing a
128Mb: x16, x32 Mobile SDRAM
t
t
RFC), once every 64ms.
RP has been met after the
©2001 Micron Technology, Inc. All rights reserved.
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