DS2788K Maxim Integrated, DS2788K Datasheet - Page 29

• Manufacturer Part Number: DS2788K
• Description: Power Management IC Development Tools
• Manufacturer: Maxim Integrated
• Series: DS2788r

The 1-Wire bus requires strict signaling protocols to
ensure data integrity. The four protocols used by the
DS2788 are as follows: the initialization sequence (reset
pulse followed by presence pulse), write-0, write-1, and
read data. All these types of signaling except the pres-
ence pulse are initiated by the bus master.
Figure 26 shows the initialization sequence required to
begin any communication with the DS2788. A presence
pulse following a reset pulse indicates that the DS2788
is ready to accept a net address command. The bus
master transmits (Tx) a reset pulse for t
master then releases the line and goes into receive
mode (Rx). The 1-Wire bus line is then pulled high by
the pullup resistor. After detecting the rising edge on
the DQ pin, the DS2788 waits for t
mits the presence pulse for t
A write-time slot is initiated when the bus master pulls
the 1-Wire bus from a logic-high (inactive) level to a
logic-low level. There are two types of write-time slots:
write-1 and write-0. All write-time slots must be t
duration with a 1µs minimum recovery time, t
Figure 26. 1-Wire Initialization Sequence
DQ
______________________________________________________________________________________
LINE TYPE LEGEND:
PDL
.
Write-Time Slots
1-Wire Signaling
PDH
BUS MASTER ACTIVE LOW
RESISTOR PULLUP
t
RSTL
Stand-Alone Fuel-Gauge IC with
and then trans-
RSTL
t
PDH
. The bus
SLOT
REC
in
,
between cycles. The DS2788 samples the 1-Wire bus
line between 15µs and 60µs (between 2µs and 6µs for
overdrive speed) after the line falls. If the line is high
when sampled, a write-1 occurs. If the line is low when
sampled, a write-0 occurs (see Figure 27). For the bus
master to generate a write-1 time slot, the bus line must
be pulled low and then released, allowing the line to be
pulled high within 15µs (2µs for overdrive speed) after
the start of the write-time slot. For the host to generate a
write-0 time slot, the bus line must be pulled low and
held low for the duration of the write-time slot.
A read-time slot is initiated when the bus master pulls
the 1-Wire bus line from a logic-high level to a logic-low
level. The bus master must keep the bus line low for at
least 1µs and then release it to allow the DS2788 to
present valid data. The bus master can then sample
the data t
end of the read-time slot, the DS2788 releases the bus
line and allows it to be pulled high by the external
pullup resistor. All read-time slots must be t
duration with a 1µs minimum recovery time, t
between cycles. See Figure 27 for more information.
t
DS2788 ACTIVE LOW
PDL
LED Display Drivers
RDV
t
RSTH
from the start of the read-time slot. By the
Read-Time Slots
PK+
PK-
SLOT
REC
29
in
,