MT48LC4M32LFF5-8:G TR Micron Technology Inc, MT48LC4M32LFF5-8:G TR Datasheet - Page 63
![IC SDRAM 128MBIT 125MHZ 90VFBGA](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32LFF5-8:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8:G TR
Description
IC SDRAM 128MBIT 125MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Specifications of MT48LC4M32LFF5-8:G TR
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 42:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
DQMU, DQML
COMMAND
A0–A9, A11
Self Refresh Mode
BA0, BA1
Notes:
CKE
A10
CLK
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
SINGLE BANK
t
PRECHARGE
ALL BANKS
AS
BANK(S)
1. No maximum time limit for self refresh.
2.
3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh
4. Self refresh is not supported on automotive temperature (AT) devices.
T0
t CKH
3b.
t CMH
t
3a. The DRAM has been in the self refresh mode for a minimum of 64ms prior to exiting.
AH
3c. At least two AUTO REFRESH commands are performed during each 15.625µs interval
t CK
t
mode until all rows have been refreshed via the AUTO REFRESH command at the distrib-
uted refresh rate, (
allowed. Self refresh mode may be reentered any time after exiting if the following condi-
tions are all met:
XSR requires a minimum of 2 clocks regardless of frequency or timing.
t
while the DRAM remains out of the self refresh mode. See Table 17 on page 53.
XSR has not been violated.
t RP
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
t
REF/number of rows), or faster. However, the following exception is
AUTO
T2
> t RAS
CLK stable prior to exiting
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self refresh mode
(Restart refresh time base)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit self refresh mode
t
RAS (MAX) only applies to non-self refresh mode.
Tn + 1
NOP
t XSR
128Mb: x16, x32 Mobile SDRAM
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To + 1
©2001 Micron Technology, Inc. All rights reserved.
To + 2
REFRESH
AUTO
Timing Diagrams
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