IS61VPS25636A-200TQLI ISSI, Integrated Silicon Solution Inc, IS61VPS25636A-200TQLI Datasheet - Page 10

• Manufacturer Part Number: IS61VPS25636A-200TQLI
• Description: IC SRAM 9MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61VPS25636A-200TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 9Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
PIN DESCRIPTIONS
10
A0, A1
A
ADSC
ADSP
ADV
BWa-BWb
BWE
CE, CE2, CE2 Synchronous Chip Enable
CLK
DQa-DQb
VDDQ
VDDQ
VDDQ
VDDQ
DQPb
VDD
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DQb
DQb
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable Option)
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Controller Address Status
Synchronous Processor Address Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Clock
Synchronous Data Input/Output
100-PIN TQFP (512K x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
DQPa-DQPb
GW
MODE
OE
V
V
Vss
ZZ
dd
ddq
DQPb
V
V
V
V
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DDQ
DDQ
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(2 Chip-Enable Option)
Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
Synchronous Global Write Enable
Burst Sequence Mode Selection
Output Enable
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
Integrated Silicon Solution, Inc.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
VSS
NC
DQPa
DQa
DQa
VSS
V
DQa
DQa
VSS
NC
V
ZZ
DQa
DQa
V
VSS
DQa
DQa
NC
NC
VSS
V
NC
NC
NC
DDQ
DDQ
DD
DDQ
DDQ
01/19/10
Rev. K